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Fix the JIT encoding of the VAForm_1 instructions, including vmaddfp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26935 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -595,8 +595,8 @@ class VAForm_1<bits<6> xo, dag OL, string asmstr,
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: I<4, OL, asmstr, itin> {
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bits<5> VD;
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bits<5> VA;
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bits<5> VB;
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bits<5> VC;
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bits<5> VB;
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let Pattern = pattern;
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@ -948,22 +948,21 @@ def RLDICR : MDForm_1<30, 1,
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let PPC970_Unit = 5 in { // VALU Operations.
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// VA-Form instructions. 3-input AltiVec ops.
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def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
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def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
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"vmaddfp $vD, $vA, $vC, $vB", VecFP,
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[(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
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VRRC:$vB))]>,
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Requires<[FPContractions]>;
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def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
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def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
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"vnmsubfp $vD, $vA, $vC, $vB", VecFP,
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[(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA,
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VRRC:$vC),
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VRRC:$vB)))]>,
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[(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC),
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VRRC:$vB)))]>,
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Requires<[FPContractions]>;
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def VPERM : VAForm_1<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
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"vperm $vD, $vA, $vB, $vC", VecPerm,
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def VPERM : VAForm_1<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
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"vperm $vD, $vA, $vC, $vB", VecPerm,
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[(set VRRC:$vD,
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(PPCvperm (v4f32 VRRC:$vA), VRRC:$vB, VRRC:$vC))]>;
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(PPCvperm (v4f32 VRRC:$vA), VRRC:$vC, VRRC:$vB))]>;
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// VX-Form instructions. AltiVec arithmetic ops.
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