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Cleanup PPC64 unaligned i64 load/store

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Remove an accidentally-added instruction definition and add a comment in the
test case. This is in response to a post-commit review by Bill Schmidt.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177404 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2013-03-19 15:23:39 +00:00
parent 037a4bcde3
commit ec2e968b7a
2 changed files with 3 additions and 4 deletions
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4
lib/Target/PowerPC/PPCInstr64Bit.td
View File

@ -683,10 +683,6 @@ def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins),
def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src),
"ldx $rD, $src", LdStLD,
[(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
let isCodeGenOnly = 1 in
def LDXu : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src),
"ldx $rD, $src", LdStLD,
[(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
let mayLoad = 1 in
def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr),

3
test/CodeGen/PowerPC/unal4-std.ll
View File

@ -17,6 +17,9 @@ vector.body.i: ; preds = %vector.body.i, %if.
if.end210: ; preds = %entry
ret void
; This will generate two align-1 i64 stores. Make sure that they are
; indexed stores and not in r+i form (which require the offset to be
; a multiple of 4).
; CHECK: @copy_to_conceal
; CHECK: stdx {{[0-9]+}}, 0,
}