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x86_64 rip-relative and magic mode address

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58528 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Mon P Wang 2008-10-31 19:13:42 +00:00
parent c072966838
commit fd532d7cd9
1 changed files with 8 additions and 4 deletions
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12
lib/Target/X86/X86CodeEmitter.cpp
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@ -338,7 +338,7 @@ void Emitter::emitMemModRMByte(const MachineInstr &MI,
unsigned BaseReg = Base.getReg();
// Is a SIB byte needed?
if (IndexReg.getReg() == 0 &&
if ((!Is64BitMode || DispForReloc) && IndexReg.getReg() == 0 &&
(BaseReg == 0 || getX86RegNum(BaseReg) != N86::ESP)) {
if (BaseReg == 0) { // Just a displacement?
// Emit special case [disp32] encoding
@ -395,9 +395,13 @@ void Emitter::emitMemModRMByte(const MachineInstr &MI,
if (BaseReg == 0) {
// Handle the SIB byte for the case where there is no base. The
// displacement has already been output.
assert(IndexReg.getReg() && "Index register must be specified!");
emitSIBByte(SS, getX86RegNum(IndexReg.getReg()), 5);
} else {
unsigned IndexRegNo;
if (IndexReg.getReg())
IndexRegNo = getX86RegNum(IndexReg.getReg());
else
IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
emitSIBByte(SS, IndexRegNo, 5);
} else {
unsigned BaseRegNo = getX86RegNum(BaseReg);
unsigned IndexRegNo;
if (IndexReg.getReg())