Commit Graph

6792 Commits

Author SHA1 Message Date
David Blaikie
0159ae4295 DebugInfo: PR14763/r183329 correct the location of indirect parameters
We had been papering over a problem with location info for non-trivial
types passed by value by emitting their type as references (this caused
the debugger to interpret the location information correctly, but broke
the type of the function). r183329 corrected the type information but
lead to the debugger interpreting the pointer parameter as the value -
the debug info describing the location needed an extra dereference.

Use a new flag in DIVariable to add the extra indirection (either by
promoting an existing DW_OP_reg (parameter passed in a register) to
DW_OP_breg + 0 or by adding DW_OP_deref to an existing DW_OP_breg + n
(parameter passed on the stack).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184368 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-19 21:55:13 +00:00
Bill Wendling
ba54bca472 Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184360 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-19 21:36:55 +00:00
Bill Wendling
f9fd58a44b Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184352 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-19 21:07:11 +00:00
Bill Wendling
ea44281d5d Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184349 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-19 20:51:24 +00:00
Jim Grosbach
a95e3091eb ARM: Add optional datatype suffix to NEON mvn asm syntax.
rdar://14194152

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184244 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-18 21:49:21 +00:00
Michael Gottesman
41502e1af7 [ARMTargetLowering] ARMISD::{SUB,ADD}{C,E} second result is a boolean implying that upper bits are always 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184231 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-18 20:49:45 +00:00
Michael Gottesman
8493edfb4b Converted an overly aggressive assert to a conditional check in AddCombineTo64bitMLAL.
Said assert assumes that ADDC will always have a glue node as its second
argument and is checked before we even know that we are actually performing the
relevant MLAL optimization. This is incorrect since on ARM we *CAN* codegen ADDC
with a use list based second argument. Thus to have both effects, I converted
the assert to a conditional check which if it fails we do not perform the
optimization.

In terms of tests I can not produce an ADDC from the IR level until I get in my
multiprecision optimization patch which is forthcoming. The tests for said patch
would cause this assert to fail implying that said tests will provide the
relevant tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184230 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-18 20:49:40 +00:00
Kevin Enderby
bf811d602d Change the arm assembler to support this from the v7c spec:
"When assembling to the ARM instruction set, the .N qualifier produces
an assembler error and the .W qualifier has no effect."

In the pre-matcher handler in the asm parser the ".w" (wide) qualifier 
when in ARM mode is now discarded. And an error message is now
produced when the ".n" (narrow) qualifier is used in ARM mode.

Test cases for these were added.

rdar://14064574


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184224 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-18 20:19:24 +00:00
David Blaikie
13769fa725 Reduce indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184213 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-18 18:03:17 +00:00
Amaury de la Vieuville
beb920fce6 ARM: fix literal load with positive offset encoding
When using a positive offset, literal loads where encoded
as if it was negative, because:
- The sign bit was not assigned to an operand
- The addrmode_imm12 operand was not encoding the sign bit correctly

This patch also makes the assembler look at the .w/.n specifier for
loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184182 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-18 08:13:05 +00:00
Amaury de la Vieuville
f8b60d6f30 ARM: add operands pre-writeback variants when needed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184181 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-18 08:12:51 +00:00
Amaury de la Vieuville
ce046b98ed ARM: fix thumb literal loads decoding
This fixes two previous issues:
- Negative offsets were not correctly disassembled
- The decoded opcodes were not the right one

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184180 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-18 08:03:06 +00:00
Amaury de la Vieuville
cea0032f73 ARM: thumb stores cannot use PC as dest register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184179 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-18 08:02:56 +00:00
Bill Wendling
99cb622041 Use pointers to the MCAsmInfo and MCRegInfo.
Someone may want to do something crazy, like replace these objects if they
change or something.

No functionality change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184175 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-18 07:20:20 +00:00
David Blaikie
0187e7a9ba DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs
Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184067 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-16 20:34:27 +00:00
David Blaikie
6d9dbd5526 Debug Info: Simplify Frame Index handling in DBG_VALUE Machine Instructions
Rather than using the full power of target-specific addressing modes in
DBG_VALUEs with Frame Indicies, simply use Frame Index + Offset. This
reduces the complexity of debug info handling down to two
representations of values (reg+offset and frame index+offset) rather
than three or four.

Ideally we could ensure that frame indicies had been eliminated by the
time we reached an assembly or dwarf generation, but I haven't spent the
time to figure out where the FIs are leaking through into that & whether
there's a good place to convert them. Some FI+offset=>reg+offset
conversion is done (see PrologEpilogInserter, for example) which is
necessary for some SelectionDAG assumptions about registers, I believe,
but it might be possible to make this a more thorough conversion &
ensure there are no remaining FIs no matter how instruction selection
is performed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184066 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-16 20:34:15 +00:00
Andrew Trick
a5ce5f36d3 Update machine models. Specify buffer sizes for OOO processors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184033 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-15 04:50:02 +00:00
Andrew Trick
b86a0cdb67 Machine Model: Add MicroOpBufferSize and resource BufferSize.
Replace the ill-defined MinLatency and ILPWindow properties with
with straightforward buffer sizes:
MCSchedMode::MicroOpBufferSize
MCProcResourceDesc::BufferSize

These can be used to more precisely model instruction execution if desired.

Disabled some misched tests temporarily. They'll be reenabled in a few commits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184032 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-15 04:49:57 +00:00
Amaury de la Vieuville
a768a49548 ARM: fix thumb coprocessor instruction with pre-writeback disassembly
was        stc2 p0, c0, [r0]!
instead of stc2 p0, c0, [r0,#0]!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183975 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-14 11:21:35 +00:00
JF Bastien
fe532ad6d6 Enable FastISel on ARM for Linux and NaCl, not MCJIT
This is a resubmit of r182877, which was reverted because it broken
MCJIT tests on ARM. The patch leaves MCJIT on ARM as it was before: only
enabled for iOS. I've CC'ed people from the original review and revert.

FastISel was only enabled for iOS ARM and Thumb2, this patch enables it
for ARM (not Thumb2) on Linux and NaCl, but not MCJIT.

Thumb2 support needs a bit more work, mainly around register class
restrictions.

The patch punts to SelectionDAG when doing TLS relocation on non-Darwin
targets. I will fix this and other FastISel-to-SelectionDAG failures in
a separate patch.

The patch also forces FastISel to retain frame pointers: iOS always
keeps them for backtracking (so emitted code won't change because of
this), but Linux was getting much worse code that was incorrect when
using big frames (such as test-suite's lencod). I'll also fix this in a
later patch, it will probably require a peephole so that FastISel
doesn't rematerialize frame pointers back-to-back.

The test changes are straightforward, similar to:
  http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130513/174279.html
They also add a vararg test that got dropped in that change.

I ran all of lnt test-suite on A15 hardware with --optimize-option=-O0
and all the tests pass. All the tests also pass on x86 make check-all. I
also re-ran the check-all tests that failed on ARM, and they all seem to
pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183966 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-14 02:49:43 +00:00
Amaury de la Vieuville
8117ac555d ARM: fix B decoding
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183914 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-13 16:41:55 +00:00
Amaury de la Vieuville
1290ce00a3 ARM: fix t2am_imm8_offset operand printing for imm=#-0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183913 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-13 16:40:51 +00:00
JF Bastien
5ab770417b ARM FastISel fix sext/zext fold
Sign- and zero-extension folding was slightly incorrect because it wasn't checking that the shift on extensions was zero. Further, I recently added AND rd, rn, #255 as a form of 8-bit zero extension, and failed to add the folding code for it.

This patch fixes both issues.

This patch fixes both, and the test should remain the same:
  test/CodeGen/ARM/fast-isel-fold.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183794 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-11 22:13:46 +00:00
NAKAMURA Takumi
6c921a55f4 Rework r183728, suppress assert(0) for now. Its behavior depends on assertions on win32 hosts.
FIXME: Introduce yet another checker but assert(0).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183736 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-11 10:01:42 +00:00
Mihai Popa
55ab7315d0 It adds support for negative zero offsets for loads and stores.
Negative zero is returned by the primary expression parser as INT32_MIN, so all that the method needs to do is to accept this value.
Behavior already present for Thumb2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183734 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-11 09:48:35 +00:00
Mihai Popa
16ad92ad3c This patch adds support for FPINST/FPINST2 as operands to vmsr/vmrs. These are optional registers that may be supported some ARM implementations to aid with resolution of floating point exceptions. The manual pages for vmsr and vmrs do not detail their use. Encodings and other information can be found in ARM Architecture Reference Manual section F, chapter 6, paragraph 3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183733 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-11 09:39:51 +00:00
Amaury de la Vieuville
aa8003712e ARM: Enforce decoding rules for VLDn instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183731 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-11 08:14:14 +00:00
Amaury de la Vieuville
3862709058 ARM: Fix STREX/LDREX reecoding
The decoded MCInst wasn't reencoded as the same instruction

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183729 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-11 08:03:20 +00:00
NAKAMURA Takumi
c139672407 Tweak a couple of tests on win32 hosts with +Asserts.
- Don't use assert(0), or tests may pass or fail according to assertions.
  - For now, The tests are marked as XFAIL for win32 hosts.

FIXME: Could we avoid XFAIL to specify triple in the RUN lines?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183728 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-11 06:52:58 +00:00
NAKAMURA Takumi
6915854dd2 ARMAsmBackend.cpp: Use Triple::isOSBinFormatCOFF() instead of isOSWindows().
FYI, isOSBinFormatCOFF() is as same as isOSWindows(), on trunk.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183727 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-11 06:52:43 +00:00
NAKAMURA Takumi
2266ef3f5e Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183726 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-11 06:52:36 +00:00
Tim Northover
9bdd785014 ARM: diagnose ARM/Thumb assembly switches on CPUs only supporting one.
Some ARM CPUs only support ARM mode (ancient v4 ones, for example) and some
only support Thumb mode (M-class ones currently). This makes sure such CPUs
default to the correct mode and makes the AsmParser diagnose an attempt to
switch modes incorrectly.

rdar://14024354

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183710 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-10 23:20:58 +00:00
Aaron Ballman
6c1bd2919e Silencing an MSVC warning about comparing signed and unsigned values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183682 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-10 16:45:40 +00:00
Amaury de la Vieuville
38946caa43 Fix misleading comments in ARMAsmParser
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183657 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-10 14:17:15 +00:00
Amaury de la Vieuville
4e9a96d810 ARM: ISB cannot be passed the same options as DMB
ISB should only accepts full system sync, other options are reserved

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183656 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-10 14:17:08 +00:00
Logan Chien
18cba562c8 Fix ARM unwind opcode assembler in several cases.
Changes to ARM unwind opcode assembler:

* Fix multiple .save or .vsave directives.  Besides, the
  order is preserved now.

* For the directives which will generate multiple opcodes,
  such as ".save {r0-r11}", the order of the unwind opcode
  is fixed now, i.e. the registers with less encoding value
  are popped first.

* Fix the $sp offset calculation.  Now, we can use the
  .setfp, .pad, .save, and .vsave directives at any order.

Changes to test cases:

* Add test cases to check the order of multiple opcodes
  for the .save directive.

* Fix the incorrect $sp offset in the test case.  The
  stack pointer offset specified in the test case was
  incorrect.  (Changed test cases: ehabi-mc-section.ll and
  ehabi-mc.ll)

* The opcode to restore $sp are slightly reordered.  The
  behavior are not changed, and the new output is same
  as the output of GNU as.  (Changed test cases:
  eh-directive-pad.s and eh-directive-setfp.s)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183627 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-09 12:22:30 +00:00
JF Bastien
1fe907e7f2 ARM FastISel fix load register classes
The register classes when emitting loads weren't quite restricting enough, leading to MI verification failure on the result register.

These are new failures that weren't there the first time I tried enabling ARM FastISel for new targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183624 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-09 00:20:24 +00:00
Amaury de la Vieuville
9eefea009f ARM: fix VMOVvnf32 decoding when ambiguous with VCVT
Enforce Table A7-15 (op=1, cmode=0b111) -> UNDEF

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183612 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-08 13:54:05 +00:00
Amaury de la Vieuville
ae50ddb2ae ARM: enforce SRS decoding constraints
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183611 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-08 13:43:59 +00:00
Amaury de la Vieuville
46e136c952 ARM: fix CPS decoding when ambiguous with QADD
Handle the case when the disassembler table can't tell
the difference between some encodings of QADD and CPS.

Add some necessary safe guards in CPS decoding as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183610 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-08 13:38:52 +00:00
Amaury de la Vieuville
c64835b0c5 ARM: fix VCVT decoding
UNPRED was reported instead of UNDEF

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183608 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-08 13:29:11 +00:00
JF Bastien
2c69e90064 Fix unused variable warning from my previous patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183601 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-08 00:51:51 +00:00
JF Bastien
8fc760cbe8 ARM FastISel integer sext/zext improvements
My recent ARM FastISel patch exposed this bug:
  http://llvm.org/bugs/show_bug.cgi?id=16178
The root cause is that it can't select integer sext/zext pre-ARMv6 and
asserts out.

The current integer sext/zext code doesn't handle other cases gracefully
either, so this patch makes it handle all sext and zext from i1/i8/i16
to i8/i16/i32, with and without ARMv6, both in Thumb and ARM mode. This
should fix the bug as well as make FastISel faster because it bails to
SelectionDAG less often. See fastisel-ext.patch for this.

fastisel-ext-tests.patch changes current tests to always use reg-imm AND
for 8-bit zext instead of UXTB. This simplifies code since it is
supported on ARMv4t and later, and at least on A15 both should perform
exactly the same (both have exec 1 uop 1, type I).

2013-05-31-char-shift-crash.ll is a bitcode version of the above bug
16178 repro.

fast-isel-ext.ll tests all sext/zext combinations that ARM FastISel
should now handle.

Note that my ARM FastISel enabling patch was reverted due to a separate
failure when dealing with MCJIT, I'll fix this second failure and then
turn FastISel on again for non-iOS ARM targets.

I've tested "make check-all" on my x86 box, and "lnt test-suite" on A15
hardware.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183551 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 20:10:37 +00:00
Bill Wendling
57148c166a Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183488 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 05:54:19 +00:00
Arnold Schwaighofer
c6752d5565 ARM sched model: Use the right resources for DIV
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183477 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 01:16:15 +00:00
Arnold Schwaighofer
873ff29514 ARM sched model: Add VFP div instruction on Swift
Reapply 183271.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183472 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 01:10:36 +00:00
Arnold Schwaighofer
7f155d7d2b ARM sched model: Add SIMD/VFP load/store instructions on Swift
Reapply 183270 again (because three is a magic number).

This should now no longer seg fault after r183459.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183464 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 00:04:28 +00:00
Arnold Schwaighofer
6b10d85303 Revert "ARM sched model: Add SIMD/VFP load/store instructions on Swift"
Breaks linux build bots (I thought the problem was something else).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183447 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 21:08:18 +00:00
Arnold Schwaighofer
5bf5b96c2b ARM sched model: Add SIMD/VFP load/store instructions on Swift
Reapply 183270.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183445 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 21:02:18 +00:00
Arnold Schwaighofer
5be946b486 ARM sched model: Add integer VFP/SIMD instructions on Swift
Reapply 183269.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183441 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 20:26:18 +00:00