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Commit Graph

156 Commits

Author SHA1 Message Date
Evan Cheng
a3ca3149f2 Add CopyCost to TargetRegisterClass. This specifies the cost of copying a value
between two registers in the specific class.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42123 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-19 01:35:01 +00:00
Dan Gohman
0fee3ff93e Add MVT::fAny for overloading intrinsics on floating-point types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41128 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-16 21:57:19 +00:00
Chandler Carruth
6994040a95 This is the patch to provide clean intrinsic function overloading support in LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future.
This also changes the syntax for llvm.bswap, llvm.part.set, llvm.part.select, and llvm.ct* intrinsics. They are automatically upgraded by both the LLVM ASM reader and the bitcode reader. The test cases have been updated, with special tests added to ensure the automatic upgrading is supported.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40807 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-04 01:51:18 +00:00
Christopher Lamb
08d52071ba Add target independent MachineInstr's to represent subreg insert/extract in MBB's. PR1350
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40518 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-26 07:48:21 +00:00
Christopher Lamb
8245510ae0 Teach TableGen about the new vector types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40513 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-26 06:41:18 +00:00
Evan Cheng
102dc195b6 No need for noResults anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40075 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-20 00:21:23 +00:00
Evan Cheng
64d80e3387 Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
Dan Gohman
3bf6e183d5 Eliminate an unused parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39828 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-13 20:16:50 +00:00
Evan Cheng
88cc092ca5 Try committing again. Add OptionalDefOperand. Remove clobbersPred.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38498 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-10 18:05:01 +00:00
Evan Cheng
c419bd3396 ImmutablePredicateOperand is no more.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37963 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-06 23:23:38 +00:00
Evan Cheng
8012b077dd Instructions with ImmutablePredicateOperand aren't really predicable since their predicates are fixed at isel time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37899 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-05 07:19:29 +00:00
Dan Gohman
d45eddd214 Revert the earlier change that removed the M_REMATERIALIZABLE machine
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37728 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-26 00:48:07 +00:00
Dan Gohman
82a87a0172 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37644 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-19 01:48:05 +00:00
Evan Cheng
eaa91b0a1f Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37643 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-19 01:26:51 +00:00
Christopher Lamb
a321125e8b Add support to tablegen for specifying subregister classes on a per register class basis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37572 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-13 22:20:15 +00:00
Evan Cheng
b5c1c9c8e3 Add clobbersPred - instruction that clobbers condition code / register which are used to predicate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37465 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-06 10:14:55 +00:00
Dan Gohman
b9daee9ece Remove the operator<< for MVT::ValueType in preparation for MVT::ValueType
being changed from an enum to an integer type, which can't have a custom
operator<< overload.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37412 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-04 16:11:03 +00:00
Evan Cheng
5127ce09a4 Rename M_PREDICATED to M_PREDICABLE; opcode can be specified isPredicable without having a PredicateOperand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37116 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-16 20:45:24 +00:00
Reid Spencer
c4de3dec62 For PR1297:
Implement code generation for overloaded intrinsic functions. The basic
difference is that "actual" argument types must be provided when
constructing intrinsic names and types. Also, for recognition, only the
prefix is examined. If it matches, the suffix is assumed to match. The
suffix is checked by the Verifier, however.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35539 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-01 07:20:02 +00:00
Bill Wendling
eebc8a1bc5 Add support for the v1i64 type. This makes better code for this:
#include <mmintrin.h>

extern __m64 C;

void baz(__v2si *A, __v2si *B)
{
  *A = C;
  _mm_empty();
}

We get this:

_baz:
        call "L1$pb"
"L1$pb":
        popl %eax
        movl L_C$non_lazy_ptr-"L1$pb"(%eax), %eax
        movq (%eax), %mm0
        movl 4(%esp), %eax
        movq %mm0, (%eax)
        emms
        ret

GCC gives us this:

_baz:
        pushl   %ebx
        call    L3
"L00000000001$pb":
L3:
        popl    %ebx
        subl    $8, %esp
        movl    L_C$non_lazy_ptr-"L00000000001$pb"(%ebx), %eax
        movl    (%eax), %edx
        movl    4(%eax), %ecx
        movl    16(%esp), %eax
        movl    %edx, (%eax)
        movl    %ecx, 4(%eax)
        emms
        addl    $8, %esp
        popl    %ebx
        ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35351 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-26 07:53:08 +00:00
Evan Cheng
04677a3b49 Recognize target instruction flag 'isReMaterializable'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35159 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-19 06:20:37 +00:00
Chris Lattner
50d456539d reapply
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34697 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-27 22:08:27 +00:00
Evan Cheng
53c9b3f68c Backing out
CodeGenTarget.cpp updated: 1.82 -> 1.83
Record.cpp updated: 1.55 -> 1.56
Record.h updated: 1.59 -> 1.60
TableGen.cpp updated: 1.47 -> 1.48
It's missing CallingConvEmitter.h


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34693 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-27 21:44:08 +00:00
Chris Lattner
798dc7adb4 initial support for calling convention generation, still unfinished.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34682 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-27 20:43:37 +00:00
Jim Laskey
a683f9ba13 Files missing from LABEL check in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33539 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-26 17:29:20 +00:00
Bill Wendling
f5da13367f What should be the last unnecessary <iostream>s in the library.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32333 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-07 22:21:48 +00:00
Evan Cheng
0555122412 Match TargetInstrInfo changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32107 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-01 22:57:41 +00:00
Chris Lattner
f64f9a4b75 Remove the isTwoAddress property from the CodeGenInstruction class. It should
not be used for anything other than backwards compat constraint handling.

Add support for a new DisableEncoding property which contains a list of
registers that should not be encoded by the generated code emitter.  Convert
the codeemitter generator to use this, fixing some PPC JIT regressions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31769 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-15 23:23:02 +00:00
Chris Lattner
0bb75004ff ADd support for adding constraints to suboperands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31748 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-15 02:38:17 +00:00
Chris Lattner
f196839562 allow ptr_rc to explicitly appear in an instructions operand list, it doesn't
have to be a subpart of a complex operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31618 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-10 02:01:40 +00:00
Chris Lattner
29434364dd emit TIED_TO correctly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31484 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-07 01:27:55 +00:00
Chris Lattner
a0cca4ae26 simplify the way operand flags and constraints are handled, making it easier
to extend.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31481 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-06 23:49:51 +00:00
Chris Lattner
a818e92f8b recognize ppc's blr instruction as predicated
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31480 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-06 21:44:54 +00:00
Evan Cheng
c51737f46f Clean up some code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31451 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-04 09:40:23 +00:00
Chris Lattner
d438b53e76 eliminate need for the NumMIOperands field in Operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31432 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-03 23:45:17 +00:00
Evan Cheng
4c2b7a3808 Tied-to constraint must be op_with_larger_idx = op_with_smaller_idx or else throw an exception.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31361 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-01 23:03:11 +00:00
Evan Cheng
e2ba897588 Add operand constraints to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31333 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-01 00:27:05 +00:00
Evan Cheng
94b3040fef Added properties such as SDNPHasChain to ComplexPattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30890 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-11 21:02:01 +00:00
Evan Cheng
d7c2c86239 Allow more use of iPTR in patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28790 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-15 00:16:37 +00:00
Evan Cheng
764811f145 Don't generate getCalleeSaveReg and getCalleeSaveRegClasses anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28376 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-18 00:08:46 +00:00
Evan Cheng
6b12516f1a Typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28366 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-17 20:55:51 +00:00
Evan Cheng
2618d07765 Remove PointerType from target definition. Use abstract type MVT::iPTR to
represent pointer type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28363 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-17 20:37:59 +00:00
Evan Cheng
44a65fa552 Allow patterns to refer to physical registers that belong to multiple
register classes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28323 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-16 07:05:30 +00:00
Chris Lattner
4b2362e247 Fix a typo: Instr* -> Intr*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
Chris Lattner
6a160fba22 Only compute intrinsic valuetypes when in a target .td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27197 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-28 00:15:00 +00:00
Chris Lattner
76f8c7c4cc revert this, it breaks things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27196 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-28 00:03:08 +00:00
Chris Lattner
8850a1bcef Add support for decoding iPTR to the right pointer type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27188 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-27 22:48:18 +00:00
Chris Lattner
2ca956f8de Make sure to initialize the TheDef field!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27078 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 20:25:01 +00:00
Chris Lattner
43fbbc36dc Move CodeGenIntrinsic implementation to CodeGenTarget.cpp with the rest of
the CodeGen* implementations.

Parse the MVT::ValueType for each operand of the intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27075 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 19:49:31 +00:00
Evan Cheng
dcfccac13b getEnumName() missed v8i8, v4i16, and v2i32 types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26869 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-19 07:57:34 +00:00
Evan Cheng
9073dea7c0 New vector type v2f32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26437 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-01 01:10:52 +00:00
Evan Cheng
aea20f50e5 Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26294 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-20 22:34:53 +00:00
Chris Lattner
aa77d77a43 PHI and INLINEASM are now builtin instructions provided by Target.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25673 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-27 01:45:06 +00:00
Evan Cheng
51fecc80f7 * Remove instruction fields hasInFlag / hasOutFlag and added SNDPInFlag and
SNDPOutFlag to DAG nodes. These properties do not belong to target specific
instructions.
* Added DAG node property SNDPOptInFlag. It's same as SNDPInFlag except it's
optional. Used by ret / call, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25154 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-09 18:27:06 +00:00
Evan Cheng
2b4ea795a2 Added field noResults to Instruction.
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25017 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-26 09:11:45 +00:00
Evan Cheng
7b05bd5814 * Support for hasInFlag and hasOutFlag (on instructions). Remove nameless FLAG
support which is fragile.
* Fixed a number of bugs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24996 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-23 22:11:47 +00:00
Evan Cheng
bcecf33dc2 Support for read / write from explicit registers with FlagVT type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24753 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-17 01:19:28 +00:00
Evan Cheng
3aa39f439a * Added an explicit type field to ComplexPattern.
* Renamed MatchingNodes to RootNodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24636 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-08 02:14:08 +00:00
Evan Cheng
0fc7198890 Added support for ComplexPattern. These are patterns that require C++ pattern
matching code that is not currently auto-generated by tblgen, e.g. X86
addressing mode. Selection routines for complex patterns can return multiple operands, e.g. X86 addressing mode returns 4.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24634 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-08 02:00:36 +00:00
Evan Cheng
1c3d19eb15 * Commit the fix (by Chris) for a tblgen type inferencing bug.
* Enhanced tblgen to handle instructions which have chain operand and writes a
chain result.
* Enhanced tblgen to handle instructions which produces no results. Part of
the change is a temporary hack which relies on instruction property (e.g.
isReturn, isBranch). The proper fix would be to change the .td syntax to
separate results dag from ops dag.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24587 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-04 08:18:16 +00:00
Nate Begeman
6510b22cec Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work.  This change has no effect on generated code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24563 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-01 04:51:06 +00:00
Nate Begeman
86193d1190 Nuke CodeGenInstruction's ValueType member, it is no longer used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24556 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-01 00:12:04 +00:00
Nate Begeman
02fc8ff800 Add the new vector types to tablegen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24514 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-29 06:19:38 +00:00
Chris Lattner
3367079b0b Initialize this variable on all paths, fixing a crasher in windows. Thanks
to JeffC for pointing this out.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24426 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-19 07:48:33 +00:00
Chris Lattner
65303d6bd7 Teach tblgen about instruction operands that have multiple MachineInstr
operands, digging into them to find register values (used on X86).  Patch
by Evan Cheng!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24424 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-19 07:05:57 +00:00
Chris Lattner
b0e103d46b Rename Record::getValueAsListDef to getValueAsListOfDefs, to more accurately
reflect what it is.
Convert some more code over to use it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24072 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-28 22:49:02 +00:00
Chris Lattner
75ee2eb4e2 Do not let getLegalValueTypes return a list with duplicates in it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23723 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-14 03:54:49 +00:00
Chris Lattner
c4a8b73ab3 force all instruction operands to be named.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23358 91177308-0d34-0410-b5e6-96231b3b80d8
2005-09-14 21:13:50 +00:00
Chris Lattner
5d7d3dba9c Check that operands have unique names. REJECT instructions with broken operand
lists: only don't parse them if they are entirely missing (sparcv9).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23355 91177308-0d34-0410-b5e6-96231b3b80d8
2005-09-14 21:05:02 +00:00
Chris Lattner
8f493130bb Add a new Record::getValueAsCode method to mirror the other getValueAs*
methods.  Use it to simplify some code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23336 91177308-0d34-0410-b5e6-96231b3b80d8
2005-09-13 21:44:28 +00:00
Chris Lattner
e9f4ba8dd4 Compute the value types that are natively supported by a target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23282 91177308-0d34-0410-b5e6-96231b3b80d8
2005-09-08 21:43:21 +00:00
Chris Lattner
e3cbf823f0 spell this right
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23099 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-26 20:55:40 +00:00
Chris Lattner
5f89bf0f9d spell this variable right
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23095 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-26 20:42:52 +00:00
Chris Lattner
8b50f9b8dc Expose a new flag to TargetInstrInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23094 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-26 20:40:46 +00:00
Chris Lattner
ac46893e24 Split register class "Methods" into MethodProtos and MethodBodies
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22928 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-19 19:12:51 +00:00
Chris Lattner
c67c18fd23 Read the namespace field from register classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22918 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-19 18:45:20 +00:00
Chris Lattner
bfd4f55202 Fix a problem jeffc noticed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22903 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-19 06:16:04 +00:00
Chris Lattner
cfbf96aa9c Figure out how many operands each instruction has, keep track of whether
or not it's variable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22885 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-18 23:38:41 +00:00
Misha Brukman
3da94aec4d Remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21428 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-22 00:00:37 +00:00
Chris Lattner
d648867173 Refactor code for numbering instructions into CodeGenTarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19758 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-22 18:58:51 +00:00
Chris Lattner
aad75aa1a2 Expose isConvertibleToThreeAddress and isCommutable bits to the code generator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19243 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-02 02:29:04 +00:00
Misha Brukman
35e83cc970 * Add option to read isLittleEndianEncoding for InstrInfo classes
* Doxygen-ify some function comments


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16974 91177308-0d34-0410-b5e6-96231b3b80d8
2004-10-14 05:50:43 +00:00
Chris Lattner
560a79f1ea Add initial support for variants. This just parses the new format, no
functionality is added


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16636 91177308-0d34-0410-b5e6-96231b3b80d8
2004-10-03 19:34:31 +00:00
Nate Begeman
cdd66b524f Add support for the isLoad and isStore flags, needed by the instruction scheduler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16554 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-28 21:01:45 +00:00
Chris Lattner
5b71d3af35 Turn the hasDelaySlot flag into the M_DELAY_SLOT_FLAG
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16553 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-28 18:38:01 +00:00
Chris Lattner
037d732e09 Alignment is now in bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15976 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-21 20:15:25 +00:00
Chris Lattner
98df506e71 Make alignment be in bits, just like size is
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15969 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-21 20:00:36 +00:00
Chris Lattner
5767775505 Support "Methods" in register classes in CodgeGenRegisterClass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15965 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-21 19:21:21 +00:00
Chris Lattner
056afeface Start parsing register classes into a more structured form
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15961 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-21 04:05:00 +00:00
Chris Lattner
7a680c6064 Read in declared reg sizes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15960 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-21 02:24:57 +00:00
Chris Lattner
2669311320 Use CodeGenRegister class to make reading in of register information more
systematic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15805 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-16 01:10:21 +00:00
Chris Lattner
175580c0f3 Make the AsmWriter a first-class tblgen object. Allow targets to specify
name of the generated asmwriter class, and the name of the format string.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15747 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-14 22:50:53 +00:00
Chris Lattner
cf03da0ce9 Start parsing more information from the Operand information
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15644 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-11 02:22:39 +00:00
Chris Lattner
552a8428fa Remove special case hacks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15643 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-11 01:53:58 +00:00
Chris Lattner
87c5905e0b Parse the operand list of the instruction. We currently support register and immediate operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15390 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-01 07:42:39 +00:00
Chris Lattner
2e1f51b8a5 Initial cut at an asm writer emitter. So far, this only handles emission of
instructions, and only instructions that take no operands at that!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15386 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-01 05:59:33 +00:00
Chris Lattner
ec3524064c Add, and start using, the CodeGenInstruction class. This class represents
an instance of the Instruction tablegen class.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15385 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-01 05:04:00 +00:00
Chris Lattner
803a5f6ecb Rename CodeGenWrappers.(cpp|h) -> CodeGenTarget.(cpp|h)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15382 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-01 04:04:35 +00:00
Chris Lattner
2082ebe8b3 Finegrainify namespacification
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15381 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-01 03:55:39 +00:00
Misha Brukman
bebdb204d2 Emit a more sensible error message if no subclasses of Target are defined.
Patch contributed by Vladimir Prus.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14010 91177308-0d34-0410-b5e6-96231b3b80d8
2004-06-04 14:59:42 +00:00