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Author SHA1 Message Date
Nick Lewycky
03dd4e8bd3 Fix typo in comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141032 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:30:08 +00:00
Bill Wendling
f7e4aefd0f Check-pointing the new SjLj EH lowering. 
This code will replace the version in ARMAsmPrinter.cpp. It creates a new
machine basic block, which is the dispatch for the return from a longjmp
call. It then shoves the address of that machine basic block into the correct
place in the function context so that the EH runtime will jump to it directly
instead of having to go through a compare-and-jump-to-the-dispatch bit. This
should be more efficient in the common case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141031 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:25:38 +00:00
Akira Hatanaka
bbb47b320d Move CHECK after entry label. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141030 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:24:30 +00:00
Akira Hatanaka
43e43f7d8b Add support for 64-bit logical NOR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141029 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:23:18 +00:00
Akira Hatanaka
2d57088ff0 Add support for 64-bit count leading ones and zeros instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141028 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:16:50 +00:00
Bill Wendling
631d11765b Move the grabbing of the jump buffer into the caller function, eliminating the need for returning a std::pair. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141026 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:15:28 +00:00
Jim Grosbach
5cd5ac6ad4 ARM assembly parsing and encoding for VMRS/FMSTAT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141025 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:12:43 +00:00
Akira Hatanaka
dda4a07cd8 Add support for 64-bit divide instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141024 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:06:13 +00:00
Devang Patel
0e6a24d92a Add C api for Instruction->eraseFromParent(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141023 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 20:59:18 +00:00
Jim Grosbach
f8bf43ec99 Update test for 141010. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141022 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 20:58:08 +00:00
Jim Grosbach
b95ed6ec46 Thumb2 ADD/SUB can take SP as a destination register. 
It's documented as a separate instruction to line up with the Thumb1
encodings, for which it really is a distinct instruction encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141020 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 20:51:59 +00:00
Akira Hatanaka
2ad766851d Clean up MipsInstrInfo::copyPhysReg and handle copies from and to 64-bit integer 
registers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141019 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 20:38:08 +00:00
Akira Hatanaka
04d3762ff1 Add support for 64-bit integer multiply instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141017 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 20:01:11 +00:00
Akira Hatanaka
36787939b2 Add definitions of instructions which move values between 64-bit integer 
registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions
of the instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141015 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 19:28:44 +00:00
Bob Wilson
ae59e8cd4d Find the strip tool that works with the specified SDKROOT. rdar://10165908 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141013 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 18:48:16 +00:00
Jim Grosbach
c82c101147 Tidy up a bit. Formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141010 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 17:59:31 +00:00
Craig Topper
581fe82c84 Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141007 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 17:28:23 +00:00
Eric Christopher
8cf5e74a9c Whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141005 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 15:49:20 +00:00
Eric Christopher
1aeb7ac624 Typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141004 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 15:49:16 +00:00
Rafael Espindola
25456ef74c Add the returns_twice attribute to LLVM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141001 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 14:45:37 +00:00
Craig Topper
04c5be9f12 Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140997 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 08:14:29 +00:00
Craig Topper
04b0b34b3a Test updates that were supposed to go with r140993. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140994 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 07:53:59 +00:00
Craig Topper
7b22976de3 Fix VEX disassembling to ignore REX.RXBW bits in 32-bit mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140993 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 07:51:09 +00:00
Nick Lewycky
1cbae18cf6 Reapply r140979 with fix! We never did get a testcase, but careful review of the 
logic by David Meyer revealed this bug.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140992 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 07:10:45 +00:00
Torok Edwin
48488a64fa attempt to fix ocaml bindings: landing pads 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140991 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 06:41:46 +00:00
Nick Lewycky
4fcc80a486 Revert r140979 due to reports of bootstrap failure. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140980 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 05:14:59 +00:00
Nick Lewycky
8fde4f5842 Add one more case we compute a max trip count. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140979 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 01:03:57 +00:00
Craig Topper
82f131a017 Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140974 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-02 21:08:12 +00:00
Craig Topper
146c6d77f0 Special case disassembler handling of REX.B prefix on NOP instruction to decode as XCHG R8D, EAX instead. Fixes PR10344. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140971 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-02 16:56:09 +00:00
Nick Lewycky
11357d4f40 Add a new icmp+select optz'n. Also shows off the load(cst) folding added in 
r140966.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140969 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-02 10:37:37 +00:00
Nick Lewycky
267236ade3 Enhance a couple places where we were doing constant folding of instructions, 
but not load instructions. Noticed by inspection.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140966 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-02 09:12:55 +00:00
Craig Topper
42fbe9aa06 Fix typo in r140954. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140962 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-02 04:54:26 +00:00
Ted Kremenek
4f101db885 Make canonicalization of ImmutableSetRef::asImmutableSet() semi-explicit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140959 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-02 01:47:07 +00:00
Craig Topper
846a2dcada Fix disassembling of INVEPT and INVVPID to take operands 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140955 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 21:20:14 +00:00
Craig Topper
e1b4a1a07e Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140954 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 19:54:56 +00:00
Chad Rosier
2bfaf521ae Revert r140924 "Attempt to fix dynamic stack realignment for thumb1 functions." 
to appease nightly testers.  Not quite there yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140953 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 19:30:36 +00:00
Nadav Rotem
cbf26e3b57 Moved type construction out of the loop and added an assert on the legality of the type. Formatted lines to the 80 char limit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140952 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 18:39:28 +00:00
Peter Collingbourne
7c78888887 Move TableGen's parser and entry point into a library 
This is the first step towards splitting LLVM and Clang's tblgen executables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140951 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 16:41:13 +00:00
Bill Wendling
2e6b97bbf8 No one should be using the method directly. Assert if they do. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140947 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 12:47:34 +00:00
Bill Wendling
405ca137a1 Add a convenience method to tell if two things are equal. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140946 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 12:44:28 +00:00
Bill Wendling
3320f2a3bf Use the ARMConstantPoolMBB class to handle the MBB values. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140943 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 09:30:42 +00:00
Bill Wendling
9c18f51daa Add ARMConstantPoolMBB to hold an MBB value in the constant pool. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140942 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 09:19:10 +00:00
Bill Wendling
14a1a6b018 Remove dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140941 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 09:05:12 +00:00
Bill Wendling
9aca75c4f8 Remove now dead methods and ivar. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140940 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 09:04:18 +00:00
Bill Wendling
fe31e67350 Use the new ARMConstantPoolSymbol class to handle external symbols. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140939 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 08:58:29 +00:00
Bill Wendling
ff4a8023ec Add an ARMConstantPool class for external symbols. This will split out the support for external symbols from the base class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140938 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 08:36:59 +00:00
Bill Wendling
3f4e4592c3 Remove now dead methods and ivar from ARMConstantPoolValue. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140937 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 08:02:05 +00:00
Bill Wendling
5bb779976a Switch over to using ARMConstantPoolConstant for global variables, functions, 
and block addresses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140936 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 08:00:54 +00:00
Bill Wendling
3e944e38ea Some more refactoring. 
* Add a couple of Create methods to the ARMConstantPoolConstant class,
* Add its own version of getExistingMachineCPValue, and
* Modify hasSameValue to return false if the object isn't an ARMConstantPoolConstant.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140935 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 07:52:37 +00:00
Bill Wendling
029e93888d Add a Create method that accepts 'kind' and 'pcadj' arguments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140934 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 06:44:24 +00:00