Commit Graph

33428 Commits

Author SHA1 Message Date
Alexei Starovoitov
04877fa7ff [bpf] fix build
Patch by Brenden Blanco.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236030 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-28 20:38:56 +00:00
Sanjay Patel
f060668270 [x86] remove RCPPS and RSQRTPS intrinsic instruction definitions
We don't need codegen-only intrinsic instructions for the vector forms of these instructions.

This makes the reciprocal estimate instruction lowering identical to how we handle normal
square roots: (V)SQRTPS / (V)SQRTPD.

No existing regression tests fail with this patch.

Differential Revision: http://reviews.llvm.org/D9301



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236013 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-28 18:48:45 +00:00
Eric Christopher
5d88757074 Add a fixme to resetTargetOptions to explain why it needs to go
away.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236009 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-28 18:09:05 +00:00
Eric Christopher
a4944e5188 Fix a [-Werror,-Winconsistent-missing-override] problem in the
NVPTX overrides.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236007 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-28 18:06:27 +00:00
Tom Stellard
53fec21fbe R600: Fix up for AsmPrinter's OutStreamer being a unique_ptr
Fixes a crash with basically any OpenGL application using the radeonsi
driver.

Patch by: Michel Dänzer

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90176
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236004 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-28 17:37:03 +00:00
Tom Stellard
1630fbeb91 R600/SI: Add a lower case alias for subtarget feature: +DumpCode
llc converts all feature strings to lower case, while the LLVM C API
does not, so we need a lower case alias in order to test this with llc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236003 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-28 17:37:00 +00:00
Justin Holewinski
0292a66bb1 [NVPTX] Handle addrspacecast constant expressions in aggregate initializers
We need to track if an AddrSpaceCast expression was seen when
generating an MCExpr for a ConstantExpr.  This change introduces a
custom lowerConstant method to the NVPTX asm printer that will create
NVPTXGenericMCSymbolRefExpr nodes at the appropriate places to encode
the information that a given symbol needs to be casted to a generic
address.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236000 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-28 17:18:30 +00:00
Sanjay Patel
2a7841dd4d move IR-level optimization flags into their own struct
This is a preliminary step to using the IR-level floating-point fast-math-flags in the SDAG (D8900).

In this patch, we introduce the optimization flags as their own struct. As noted in the TODO comment, 
we should eventually share this data between the IR passes and the backend.

We also switch the existing nsw / nuw / exact bit functionality of the BinaryWithFlagsSDNode class to
use the new struct.

The tradeoff is that instead of using the free but limited space of SDNode's SubclassData, we add a
data member to the subclass. This means we don't have to repeat all of the get/set methods per flag,
but we're potentially adding size to all nodes of this subclassi type.

In practice on 64-bit systems (measured on Linux and MacOS X), there is no size difference between an
SDNode and BinaryWithFlagsSDNode after this change: they're both 80 bytes. This means that we had at
least one free byte to play with due to struct alignment.

Differential Revision: http://reviews.llvm.org/D9325



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235997 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-28 16:39:12 +00:00
Elena Demikhovsky
83259d70bb Fixed crash of variable shift inst on AVX2
https://llvm.org/bugs/show_bug.cgi?id=22955



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235993 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-28 14:46:35 +00:00
Toma Tabacu
8bec0f9db1 [mips] [IAS] Do not generate redundant ORi in createLShiftOri.
Summary: If the immediate is 0, the ORi is pointless.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8969

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235990 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-28 14:06:35 +00:00
Sergey Dmitrouk
1f7a90d793 Reapply r235977 "[DebugInfo] Add debug locations to constant SD nodes"
[DebugInfo] Add debug locations to constant SD nodes

This adds debug location to constant nodes of Selection DAG and updates
all places that create constants to pass debug locations
(see PR13269).

Can't guarantee that all locations are correct, but in a lot of cases choice
is obvious, so most of them should be. At least all tests pass.

Tests for these changes do not cover everything, instead just check it for
SDNodes, ARM and AArch64 where it's easy to get incorrect locations on
constants.

This is not complete fix as FastISel contains workaround for wrong debug
locations, which drops locations from instructions on processing constants,
but there isn't currently a way to use debug locations from constants there
as llvm::Constant doesn't cache it (yet). Although this is a bit different
issue, not directly related to these changes.

Differential Revision: http://reviews.llvm.org/D9084

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235989 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-28 14:05:47 +00:00
Daniel Jasper
515cc265c9 Revert "[DebugInfo] Add debug locations to constant SD nodes"
This breaks a test:
http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/23870

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235987 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-28 13:38:35 +00:00
Toma Tabacu
f9fc545757 [mips] [IAS] Rename the createShiftOr function to createLShiftOri. NFC.
Summary: The new name is more accurate with regard to the functionality.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8968

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235984 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-28 13:16:06 +00:00
Toma Tabacu
c3adf30a03 [mips] [IAS] Store the expandLoadImm destination register in a variable. NFC.
Summary: This removes multiple calls to getReg() and saves us column space in the source file.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8924

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235978 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-28 12:04:53 +00:00
Sergey Dmitrouk
716c5d8a30 [DebugInfo] Add debug locations to constant SD nodes
This adds debug location to constant nodes of Selection DAG and updates
all places that create constants to pass debug locations
(see PR13269).

Can't guarantee that all locations are correct, but in a lot of cases choice
is obvious, so most of them should be. At least all tests pass.

Tests for these changes do not cover everything, instead just check it for
SDNodes, ARM and AArch64 where it's easy to get incorrect locations on
constants.

This is not complete fix as FastISel contains workaround for wrong debug
locations, which drops locations from instructions on processing constants,
but there isn't currently a way to use debug locations from constants there
as llvm::Constant doesn't cache it (yet). Although this is a bit different
issue, not directly related to these changes.

Differential Revision: http://reviews.llvm.org/D9084

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235977 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-28 11:56:37 +00:00
Elena Demikhovsky
44a0c9071a AVX-512: Added "pandn" intrinsics set
by Asaf Badouh (asaf.badouh@intel.com)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235971 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-28 08:12:42 +00:00
Ahmed Bougacha
e1f835ab59 [MC] Use LShr for constant evaluation of ">>" on ELF/arm64--darwin.
This matches other assemblers and is less unexpected (e.g. PR23227).
On ELF, I tried binutils gas v2.24 and nasm 2.10.09, and they both
agree on LShr.  On COFF, I couldn't get my hands on an assembler yet,
so don't change the behavior.  For now, don't change it on non-AArch64
Darwin either, as the other assembler is gas v1.38, which does an AShr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235963 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-28 01:37:11 +00:00
Matthias Braun
0dff695ba9 Cleanup, remove unused return value
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235952 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-28 00:37:05 +00:00
Sanjay Patel
fd55d49f65 remove obsolete pattern matches for scalar SSE ops
The blendi pattern should always replace the insertps pattern after:
http://reviews.llvm.org/rL232850
http://reviews.llvm.org/rL235124



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235930 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-27 22:23:17 +00:00
Ahmed Bougacha
ae618e7873 [AArch64] Also combine vector selects fed by non-i1 SETCCs.
After legalization, scalar SETCC has an i32 result type on AArch64.
The i1 requirement seems too conservative, replace it with an assert.

This also means that we now can run after legalization. That should also
be fine, since the ops legalizer runs again after each combine, and
all types created all have the same sizes as the (legal) inputs.

Exposed by r235917; while there, robustize its tests (bsl also uses the
register it defines).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235922 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-27 21:43:12 +00:00
Ahmed Bougacha
bc92b2ca37 [AArch64] Don't assert when combining (v3f32 select (setcc f64)).
When the setcc has f64 operands, we can't build a vector setcc mask
to feed a vselect, because f64 doesn't divide v3f32 evenly.
Just bail out when that happens.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235917 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-27 21:01:20 +00:00
Bill Schmidt
445b1c78a5 Silence unused variable errors for no-asserts builds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235913 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-27 20:22:35 +00:00
Bill Schmidt
dcc4f724cc [PPC64LE] Remove unnecessary swaps from lane-insensitive vector computations
This patch adds a new SSA MI pass that runs on little-endian PPC64
code with VSX enabled. Loads and stores of 4x32 and 2x64 vectors
without alignment constraints are accomplished for little-endian using
lxvd2x/xxswapd and xxswapd/stxvd2x. The existence of the additional
xxswapd instructions hurts performance in comparison with big-endian
code, but they are necessary in the general case to support correct
semantics.

However, the general case does not apply to most vector code. Many
vector instructions are lane-insensitive; they do not "care" which
lanes the parallel computations are performed within, provided that
the resulting data is stored into the correct locations. Thus this
pass looks for computations that perform only lane-insensitive
operations, and remove the unnecessary swaps from loads and stores in
such computations.

Future improvements will allow computations using certain
lane-sensitive operations to also be optimized in this manner, by
modifying the lane-sensitive operations to account for the permuted
order of the lanes. However, this patch only adds the infrastructure
to permit this; no lane-sensitive operations are optimized at this
time.

This code is heavily exercised by the various vectorizing applications
in the projects/test-suite tree. For the time being, I have only added
one simple test case to demonstrate what the pass is doing. Although
it is quite simple, it provides coverage for much of the code,
including the special case handling of copies and subreg-to-reg
operations feeding the swaps. I plan to add additional tests in the
future as I fill in more of the "special handling" code.

Two existing tests were affected, because they expected the swaps to
be present, but they are now removed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235910 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-27 19:57:34 +00:00
Sanjay Patel
95619d83af fix 80-cols; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235902 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-27 17:45:44 +00:00
Sanjay Patel
4e9cdece79 fix typos; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235896 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-27 17:03:31 +00:00
Toma Tabacu
b363a5846d [mips] Correct bytes to bits in 2 comments. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235891 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-27 15:21:38 +00:00
Elena Demikhovsky
f8ae1af2e1 AVX-512: added calling conventions for i1 vectors.
Fixed bug: https://llvm.org/bugs/show_bug.cgi?id=20724



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235889 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-27 15:11:19 +00:00
Brendon Cahoon
2afd045e03 [Hexagon] Use constant extenders to fix up hardware loops
Use a loop instruction with a constant extender for a hardware
loop instruction that is too far away from the start of the loop.
This is cheaper than changing the SA register value.

Differential Revision: http://reviews.llvm.org/D9262


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235882 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-27 14:16:43 +00:00
Toma Tabacu
af3ec2cfd4 [mips] [IAS] Improve warning for using AT with .set noat.
Summary:
Changed the warning message to show the current value of $at, similar to what clang does for typedef's, and renamed warnIfAssemblerTemporary to a more descriptive name.

I also changed the type of variables which store registers from int to unsigned, updated the relevant test and tried to make the related comments clearer.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8479

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235881 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-27 14:05:04 +00:00
Vasileios Kalintiris
659d53e897 Reapply "[mips][FastISel] Implement shift ops for Mips fast-isel.""
This reapplies r235194, which was reverted in r235495 because it was causing a
failure in our out-of-tree buildbots for MIPS. With the sign-extension patch
in r235718, this patch doesn't cause any problem any more.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235878 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-27 13:28:05 +00:00
Toma Tabacu
23c4ea3fda [mips] [IAS] Rename getATRegNum and setATReg to {g,s}etATRegIndex. NFC.
Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8480

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235877 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-27 13:12:59 +00:00
Elena Demikhovsky
17bbdd05dd AVX-512: Extend/Truncate operations for SKX,
SETCC for bit-vectors



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235875 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-27 12:57:59 +00:00
Simon Pilgrim
6df35e7844 [X86][SSE] Add v16i8/v32i8 multiplication support
Patch to allow int8 vectors to be multiplied on the SSE unit instead of being scalarized.

The patch sign extends the i8 lanes to i16, uses the SSE2 pmullw multiplication instruction, then packs the lower byte from each result.

Differential Revision: http://reviews.llvm.org/D9115

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235837 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-27 07:55:46 +00:00
Alexei Starovoitov
ad82d26669 [bpf] fix build and remove a compiler warning in Release mode
Patch by Brenden Blanco.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235814 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-26 01:58:08 +00:00
Benjamin Kramer
b6ee10d9e5 [ARM] Simplify code. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235803 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-25 17:25:13 +00:00
Benjamin Kramer
4b86b0db83 [hexagon] Use range-based for loops. No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235802 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-25 14:46:53 +00:00
Benjamin Kramer
79408c7dc8 [hexagon] Remove setHexLibcallName, it leaks memory.
Just spell out the full names, it's not that much more code.
No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235801 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-25 14:46:46 +00:00
Lang Hames
579cebfb15 [AsmPrinter] Make AsmPrinter's OutStreamer member a unique_ptr.
AsmPrinter owns the OutStreamer, so an owning pointer makes sense here. Using a
reference for this is crufty.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235752 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-24 19:11:51 +00:00
Vasileios Kalintiris
7739394dad [mips][FastISel] Specify which types we handle for integer extension.
Summary:
Perform integer extension only when the destination type is one of
i8, i16 & i32 and when the source type is i1, i8 or i16. For other
combinations we fall back to SelectionDAG.

This fixes the test MultiSource/Benchmarks/7zip that was failing in our
out-of-tree MIPS buildbots.

Reviewers: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9243

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235718 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-24 13:48:19 +00:00
Jingyue Wu
728ad0157c Resurrect r235688
We should skip vector types which are not SCEVable.

test/CodeGen/NVPTX/sched2.ll passes


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235695 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-24 04:22:39 +00:00
Jingyue Wu
f42450abb6 Revert r235688
Seems breaking builds


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235690 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-24 03:26:11 +00:00
Jingyue Wu
b55e9545f2 [NVPTX] Emits "generic()" depending on the original address space
Summary:
Fixes a bug in the NVPTX codegen. The code used to miss necessary "generic()"
on aggregates of addrspacecasts.

Test Plan: addrspacecast-gvar.ll

Reviewers: eliben, jholewinski

Reviewed By: jholewinski

Subscribers: jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D9130

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235689 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-24 02:57:30 +00:00
Jingyue Wu
d83b3b1a8d [NVPTX] enable NaryReassociate in NVPTX
Summary:
We run NaryReassociate right after SLSR because SLSR enables many
opportunities for NaryReassociate. For example, in nary-slsr.ll

  foo((a + b) + c);
  foo((a + b * 2) + c);
  foo((a + b * 3) + c);   // 2 muls and 6 adds

after SLSR:

  ab = a + b;
  foo(ab + c);
  ab2 = ab + b;
  foo(ab2 + c);
  ab3 = ab2 + b;
  foo(ab3 + c);           // 6 adds

after NaryReassociate:

  abc = (a + b) + c;
  foo(abc);
  ab2c = abc + b;
  foo(ab2c);
  ab3c = ab2c + b;
  foo(ab3c);              // 4 adds

Test Plan: nary-slsr.ll

Reviewers: jholewinski, eliben

Reviewed By: eliben

Subscribers: jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D9066

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235688 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-24 02:54:06 +00:00
Matt Arsenault
9dd5b1fbd8 R600/SI: Fix verifier error when producing v_madmk_f32
Copy the kill flags when swapping the operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235687 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-24 01:57:58 +00:00
Matthias Braun
bd112c28b5 R600/RegisterCoalescer: Enable more rematerialization/add missing testcase
This enables the rematerialization of some R600 MOV instructions in the
RegisterCoalescer and adds a testcase for r235668.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235675 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-24 00:25:50 +00:00
Matt Arsenault
784f73714b R600/SI: Special case v_mov_b32 as really rematerializable
This should be fixed to properly understand all rematerializable
instructions while ignoring implicit reads of exec.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235671 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 23:34:48 +00:00
Hal Finkel
100eab89f5 [PowerPC] Support register name prefixes for vector registers
Match binutils by supporting the optional register name prefix for new vector
registers ("vs" for VSX registers and "q" for QPX registers).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235665 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 23:16:22 +00:00
Hal Finkel
ba03f542ac [PowerPC] Use sync inst alias when printing
So long as the choice between printing msync and sync is not ambiguous, we can
print 'sync 0' and just 'sync'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235663 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 23:05:08 +00:00
Tom Stellard
6d49b023a4 R600: Correctly lower CONCAT_VECTOR nodes with more than 2 operands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235662 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 22:59:24 +00:00
Hal Finkel
79f43b2736 [PowerPC] Add asm/disasm support for dcbt with hint
Add assembler/disassembler support for dcbt/dcbtst (and aliases) with the hint
field specified (non-zero). Unforunately, the syntax for this instruction is
special in that it differs for server vs. embedded cores:
   dcbt ra, rb, th [server]
   dcbt th, ra, rb [embedded]
where th can be omitted when it is 0. dcbtst is the same. Thus we need to play
games in the parser and the printer to flip the operands around on the embedded
cores. We'll use the server syntax as the default (binutils currently uses the
embedded form by default, but IBM is changing that).

We also stop marking dcbtst as having unmodeled side effects (this is not
necessary, it is just a hint like dcbt -- noticed by inspection, so no separate
test case).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235657 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 22:47:57 +00:00