Dan Gohman
d35121ad00
Fix a tblgen problem handling variable_ops in tblgen instruction
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definitions. This adds a new construct, "discard", for indicating
that a named node in the input matching pattern is to be discarded,
instead of corresponding to a node in the output pattern. This
allows tblgen to know where the arguments for the varaible_ops are
supposed to begin.
This fixes "rdar://5791600", whatever that is ;-).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51699 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-29 19:57:41 +00:00
Dan Gohman
21323f3a82
Expand small memmovs using inline code. Set the X86 threshold for expanding
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memmove to a more plausible value, now that it's actually being used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51696 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-29 19:42:22 +00:00
Evan Cheng
f26ffe987c
Implement vector shift up / down and insert zero with ps{rl}lq / ps{rl}ldq.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51667 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-29 08:22:04 +00:00
Bill Wendling
75cf88f1fe
XOR?RI instructions aren't as cheap as moves.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51664 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-29 03:46:36 +00:00
Bill Wendling
bd0879d7d9
Implement "AsCheapAsAMove" for some obviously cheap instructions: xor and the
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like.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51662 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-29 01:02:09 +00:00
Bill Wendling
8370d38ade
Add a flag to indicate that an instruction is as cheap (or cheaper) than a move
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instruction to execute. This can be used for transformations (like two-address
conversion) to remat an instruction instead of generating a "move"
instruction. The idea is to decrease the live ranges and register pressure and
all that jazz.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51660 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-28 22:54:52 +00:00
Nate Begeman
73e4d594e7
Update some comments noticed in a recent checkin
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51644 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-28 16:31:36 +00:00
Chris Lattner
e5ab3355ba
Add chain inputs for loads.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51635 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-28 04:25:57 +00:00
Chris Lattner
3f1891ca6d
Fix CodeGen/Generic/2005-10-21-longlonggtu.ll on ia64.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51634 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-28 04:14:30 +00:00
Chris Lattner
b0349bfe72
loads should get chains. THis helps but does not solve CodeGen/Generic/2003-05-27-phifcmpd.ll
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on ia64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51633 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-28 04:06:52 +00:00
Chris Lattner
9b07d3d378
Fix 2006-04-28-Sign-extend-bool.ll for ia64.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51632 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-28 04:00:06 +00:00
Chris Lattner
aec8d823fb
reindent.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51631 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-28 03:59:32 +00:00
Dan Gohman
c2ecdc5a26
Fix the encoding for two more "rm" instructions that were using MRMSrcReg.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51630 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-28 01:50:19 +00:00
Mon P Wang
bfbbd4d221
Fixed X86 encoding error CVTPS2PD and CVTPD2PS when the source operand
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is a memory location
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51626 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-28 00:42:27 +00:00
Nate Begeman
f7333bf4a2
Don't attempt to create VZEXT_LOAD out of an extload. This an issue where the
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code generator would do something like this:
f64 = load f32 <anyext>, f32mem
v2f64 = insertelt undef, %0, 0
v2f64 = insertelt %1, 0.0, 1
into
v2f64 = vzext_load f32mem
which on x86 is movsd, when you really wanted a cvtss2sd/movsd pair.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51624 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-28 00:24:25 +00:00
Duncan Sands
43e2a03530
Fix some constructs that gcc-4.4 warns about.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51591 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-27 11:50:51 +00:00
Chris Lattner
e7a83dfac6
Add FreeBSD/PPC support, patch by Marcel Moolenaar!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51538 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-24 04:58:48 +00:00
Evan Cheng
a31593901d
Eliminate x86.sse2.punpckh.qdq and x86.sse2.punpckl.qdq.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51533 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-24 02:56:30 +00:00
Evan Cheng
e716bb1c59
Eliminate x86.sse2.movs.d, x86.sse2.shuf.pd, x86.sse2.unpckh.pd, and x86.sse2.unpckl.pd intrinsics. These will be lowered into shuffles.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51531 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-24 02:14:05 +00:00
Duncan Sands
5ea38a6144
Tweak how ConstantFP80Ty constants are output
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so that gcc doesn't warn about them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51529 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-24 01:00:52 +00:00
Dale Johannesen
247580b569
Put initialized const weak objects into correct
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sections on ppc32 darwin. g++.dg/abi/key2.C
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51527 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-24 00:10:20 +00:00
Evan Cheng
fe5b159ae2
This is done.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51526 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-24 00:10:13 +00:00
Evan Cheng
999dbe6bbc
Remove x86.sse2.loadh.pd and x86.sse2.loadl.pd. These will be lowered into load and shuffle instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51522 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-24 00:07:29 +00:00
Dale Johannesen
80d7e26513
Add a missed CommonLinkage check.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51503 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-23 21:33:27 +00:00
Evan Cheng
cd0baf21a1
Use movlps / movhps to modify low / high half of 16-byet memory location.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51501 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-23 21:23:16 +00:00
Dan Gohman
a9e75631a7
Elaborate on the entry on integer vector multiplication by constants.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51491 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-23 18:05:39 +00:00
Evan Cheng
50f778deed
Fix a duplicated pattern.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51490 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-23 18:00:18 +00:00
Dan Gohman
0b924dcef8
Use PMULDQ for v2i64 multiplies when SSE4.1 is available. And add
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load-folding table entries for PMULDQ and PMULLD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51489 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-23 17:49:40 +00:00
Evan Cheng
d4083d01d2
New entry.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51487 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-23 17:28:11 +00:00
Dan Gohman
17dab19226
Fix another isFirstClassType that now needs to be isSingleValueType.
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This fixes recent CBE regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51483 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-23 16:57:00 +00:00
Chris Lattner
3adaa93700
we compile multiply-by-constant into horrible code. Doesn't sse4 have some
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instruction for doing this?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51473 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-23 04:29:53 +00:00
Evan Cheng
b1938263c7
Bug: rcpps can only folds a load if the address is 16-byte aligned. Fixed many 'ps' load folding patterns in X86InstrSSE.td which are missing the proper alignment checks.
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Also fixed some 80 col. violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51462 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-23 00:37:07 +00:00
Dale Johannesen
bbcb34cafb
Put const weak stuff in appropriate section on Darwin.
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g++.dg/abi/key2.C
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51458 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-23 00:16:59 +00:00
Evan Cheng
5bbaf01b84
X86CodeEmitter should not set PIC style to None at initialization time. This will break codegen if relocation model is changed to PIC_ later.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51455 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-22 23:55:24 +00:00
Evan Cheng
c36c0ab44b
Add missing patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51435 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-22 18:56:56 +00:00
Chris Lattner
687a4cb295
fix an off-by-one error in my previous patch, don't treat the callee as a incoming arg.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51422 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-22 06:29:38 +00:00
Chris Lattner
f6a048c3a8
Add support for multiple-return values in inline asm. This should
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get inline asm working as well as it did previously with the CBE
with the new MRV support for inline asm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51420 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-22 06:19:37 +00:00
Evan Cheng
8e8de684c7
movsd and movq do not require 16-byte alignment. This fixes vec_set-5.ll on Linux.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51327 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-20 18:24:47 +00:00
Evan Cheng
a125e62117
runOnMachineFunction should set IsPIC because relocation model may have been changed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51291 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-20 01:56:59 +00:00
Dale Johannesen
c215b3ef5d
Handle quoted names when constructing $stub's,
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$non_lazy_ptr's and $lazy_ptr's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51277 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-19 21:38:18 +00:00
Chris Lattner
b5783106c4
trip count computation deficiency
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51222 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-17 15:37:38 +00:00
Dale Johannesen
ea7dd40714
Record weak external linkage in a case where we were
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missing it. gcc.dg/darwin-weakimport-2.c.
Handle common and weak differently for darwin ppc32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51201 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-16 20:09:25 +00:00
Gabor Greif
7cbd8a3e92
API change for {BinaryOperator|CmpInst|CastInst}::create*() --> Create. Legacy interfaces will be in place for some time. (Merge from use-diet branch.)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51200 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-16 19:29:10 +00:00
Dale Johannesen
f88c81e332
Treat common as distinct from weak global on Darwin x86.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51172 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-16 00:52:06 +00:00
Evan Cheng
0ef8de30fa
Fix typos and comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51165 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-15 22:13:02 +00:00
Evan Cheng
f0df03134e
Make use of vector load and store operations to implement memcpy, memmove, and memset. Currently only X86 target is taking advantage of these.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51140 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-15 08:39:06 +00:00
Evan Cheng
bb60674191
Silence warnings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51129 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-14 20:33:21 +00:00
Dale Johannesen
aafce77b17
Add CommonLinkage; currently tentative definitions
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are represented as "weak", but there are subtle differences
in some cases on Darwin, so we need both. The intent
is that "common" will behave identically to "weak" unless
somebody changes their target to do something else.
No functional change as yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51118 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-14 20:12:51 +00:00
Sanjiv Gupta
2010b3eea6
Detabification. Fixed indentation and spacing.
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Changed cout to DOUT, and TODOs to FIXMEs.
Other changes as per coding conventions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51105 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-14 11:31:39 +00:00
Nicolas Geoffray
9474ede38b
Fix typo in ParameterAttribute fields usage. Add an include
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to make the Cpp backend output compilable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51095 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-14 07:52:03 +00:00
Sanjiv Gupta
2d4e7f732a
Fixed the file description header at the top to remove the developer name.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51094 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-14 06:50:01 +00:00
Evan Cheng
6bf877035e
Doh. Alignment is in bytes, not in bits.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51092 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-14 02:49:43 +00:00
Dan Gohman
c9f5f3f64f
Change target-specific classes to use more precise static types.
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This eliminates the need for several awkward casts, including
the last dynamic_cast under lib/Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51091 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-14 01:58:56 +00:00
Chris Lattner
3b34e1e9e8
add a note
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51062 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-13 19:56:20 +00:00
Evan Cheng
b656443366
- Fix the pasto in the fix for a previous pasto.
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- Incorporate Chris' comment suggestion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51061 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-13 18:59:59 +00:00
Chris Lattner
7171c836a9
add a note
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51060 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-13 18:48:54 +00:00
Nate Begeman
32097bdbf6
Fix one more encoding bug.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51057 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-13 17:52:09 +00:00
Evan Cheng
11b6793ede
- Don't treat anyext 16-bit load as a 32-bit load if it's volatile.
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- Correct a pasto.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51054 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-13 16:45:56 +00:00
Sanjiv Gupta
0e68771536
Adding files for Microchip's PIC16 target.
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A brief description about PIC16:
===============================
PIC16 is an 8-bit microcontroller with only one 8-bit register which is the
accumulator. All arithmetic/load/store operations are 8-bit only.
The architecture has two address spaces: program and data. The program memory
is divided into 2K pages and the data memory is divided into banks of 128 byte, with only 80 usable bytes, resulting in an non-contiguous data memory.
It supports direct data memory access (by specifying the address as part of the instruction) and indirect data and program memory access (in an unorthodox fashion which utilize a 16 bit pointer register).
Two classes of registers exist: (8-bit class which is only one
accumulator) (16-bit class, which contains one or more 16 bit
pointer(s))
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51027 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-13 09:02:57 +00:00
Evan Cheng
77f0b7a50a
Instead of a vector load, shuffle and then extract an element. Load the element from address with an offset.
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pshufd $1, (%rdi), %xmm0
movd %xmm0, %eax
=>
movl 4(%rdi), %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51026 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-13 08:35:03 +00:00
Nate Begeman
c9bdb00683
Fix and encoding error in the psrad xmm, imm8 instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51020 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-13 01:47:52 +00:00
Evan Cheng
fa7fd33a26
On x86, it's safe to treat i32 load anyext as a normal i32 load. Ditto for i8 anyext load to i16.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51019 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-13 00:54:02 +00:00
Dan Gohman
844731a7f1
Clean up the use of static and anonymous namespaces. This turned up
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several things that were neither in an anonymous namespace nor static
but not intended to be global.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51017 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-13 00:00:25 +00:00
Nate Begeman
0d1704b955
Teach Legalize how to scalarize VSETCC
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Teach X86 a few more vsetcc patterns. Custom lowering for unsupported ones is next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51009 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-12 23:09:43 +00:00
Evan Cheng
9bfa03c6fd
Xform bitconvert(build_pair(load a, load b)) to a single load if the load locations are at the right offset from each other.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51008 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-12 23:04:07 +00:00
Bill Wendling
9f8fea3531
Constify the machine instruction passed into the
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"is{Trivially,Really}ReMaterializable" methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51001 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-12 20:54:26 +00:00
Nate Begeman
c2616e43fd
Initial X86 codegen support for VSETCC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51000 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-12 20:34:32 +00:00
Dan Gohman
9499b7186b
Fix a copy+paste bug; pseudo-instructions shouldn't have
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encoding information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50997 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-12 20:22:45 +00:00
Evan Cheng
ad4196b44a
Refactor isConsecutiveLoad from X86 to TargetLowering so DAG combiner can make use of it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50991 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-12 19:56:52 +00:00
Nate Begeman
b43e9c1965
Add support for vicmp/vfcmp codegen, more legalize support coming.
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This is necessary to unbreak the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50988 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-12 19:40:03 +00:00
Dan Gohman
2ce3898e41
Fix a compile error on compilers that still want a return value
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in a non-void function that calls abort.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50969 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-12 16:17:19 +00:00
Anton Korobeynikov
64d69102a1
Add note
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50959 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-11 14:33:15 +00:00
Evan Cheng
50d9e7289b
When transforming a vector_shuffle to a load, the base address must not be an undef.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50940 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-10 06:46:49 +00:00
Dan Gohman
9018e836fe
For now, abort when an ISD::VAARG is encountered on x86-64, rather
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than silently generate invalid code.
llvm-gcc does not currently use VAArgInst; it lowers va_arg in the
front-end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50930 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-10 01:26:14 +00:00
Evan Cheng
b70ea0bd03
Some clean up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50929 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-10 00:59:18 +00:00
Evan Cheng
25210da757
If movl top bits are undef, let it be selected to movlps, etc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50928 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-10 00:58:41 +00:00
Evan Cheng
23573e5be6
Add a pattern to do move the low element of a v4f32 and zero extend the rest.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50922 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-09 23:37:55 +00:00
Evan Cheng
d880b97257
Handle a few more cases of folding load i64 into xmm and zero top bits.
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Note, some of the code will be moved into target independent part of DAG combiner in a subsequent patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50918 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-09 21:53:03 +00:00
Evan Cheng
fd17f42bab
Use movq to move low half of XMM register and zero-extend the rest.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50874 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-08 22:35:02 +00:00
Evan Cheng
7e2ff77ef0
Handle vector move / load which zero the destination register top bits (i.e. movd, movq, movss (addr), movsd (addr)) with X86 specific dag combine.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50838 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-08 00:57:18 +00:00
Duncan Sands
671fa97a4b
Output correct exception handling and frame info
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on x86-64 linux. This causes no regressions on
32 bit linux and 32 bit ppc. More tests pass
on 64 bit ppc with no regressions. I didn't
turn on eh on 64 bit linux because the intrinsics
needed to compile the eh runtime aren't done
yet. But if you turn it on and link with the
mainline runtime then eh seems to work fine
on x86-64 linux with this patch. Thanks to
Dale for testing. The main point of the patch
is that if you output that some object is
encoded using 4 bytes you had better not output
8 bytes for it: the patch makes everything
consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50825 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-07 19:11:09 +00:00
Chris Lattner
3bf6accfea
Match things like 'armv5tejl-unknown-linux-gnu' for PR2290
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50698 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-06 02:29:28 +00:00
Dan Gohman
4a3f6c8882
Make several variable declarations static.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50696 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-06 01:53:16 +00:00
Chris Lattner
88c1baa50c
add a micro optzn.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-05 23:19:45 +00:00
Mon P Wang
ab3e747c64
Improved generated code for atomic operators
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50677 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-05 22:56:23 +00:00
Evan Cheng
71f489d728
Code clean up. No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50675 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-05 22:12:23 +00:00
Mon P Wang
63307c335a
Added addition atomic instrinsics and, or, xor, min, and max.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50663 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-05 19:05:59 +00:00
Dan Gohman
94bbdc8c25
Fix IsLinux being uninitialized on non-Linux targets.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50660 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-05 18:43:07 +00:00
Anton Korobeynikov
aa57a7f7a1
Fix 80col violation
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50654 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-05 17:08:59 +00:00
Dan Gohman
600bf16cf7
Use a dedicated IsLinux flag instead of an ELFLinux TargetType.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50649 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-05 16:11:31 +00:00
Dan Gohman
a779a9899a
Add AsmPrinter support for emitting a directive to declare that
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the code being generated does not require an executable stack.
Also, add target-specific code to make use of this on Linux
on x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50634 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-05 00:28:39 +00:00
Anton Korobeynikov
6625eff8ec
Add General Dynamic TLS model for X86-64. Some parts looks really ugly (look for tlsaddr pattern),
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but should work. Work is in progress, more models will follow
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50630 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-04 21:36:32 +00:00
Evan Cheng
5759f97f50
Select vector shift with non-immediate i32 shift amount operand by first moving the operand into the right register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50619 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-04 09:15:50 +00:00
Evan Cheng
22b942aa4d
Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50601 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-03 00:52:09 +00:00
Evan Cheng
082f1161b1
Undo r50574. We are already ensuring the folded load address is 16-byte aligned.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50578 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-02 17:01:01 +00:00
Evan Cheng
b609339a5c
80 column violation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50575 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-02 07:53:32 +00:00
Evan Cheng
ef6a512489
Not safe folding a load + FsXORPSrr into FsXORPSrm. It's loading a FR64 value but the load folding variant expects a 16-byte aligned address.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50574 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-02 07:50:58 +00:00
Arnold Schwaighofer
30e62c098b
Tail call optimization improvements:
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Move platform independent code (lowering of possibly overwritten
arguments, check for tail call optimization eligibility) from
target X86ISelectionLowering.cpp to TargetLowering.h and
SelectionDAGISel.cpp.
Initial PowerPC tail call implementation:
Support ppc32 implemented and tested (passes my tests and
test-suite llvm-test).
Support ppc64 implemented and half tested (passes my tests).
On ppc tail call optimization is performed if
caller and callee are fastcc
call is a tail call (in tail call position, call followed by ret)
no variable argument lists or byval arguments
option -tailcallopt is enabled
Supported:
* non pic tail calls on linux/darwin
* module-local tail calls on linux(PIC/GOT)/darwin(PIC)
* inter-module tail calls on darwin(PIC)
If constraints are not met a normal call will be emitted.
A test checking the argument lowering behaviour on x86-64 was added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50477 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-30 09:16:33 +00:00
Scott Michel
203b2d6eed
Bug fixes and updates for CellSPU, syncing up with trunk. Most notable
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fixes are target-specific lowering of frame indices, fix constants generated
for the FSMBI instruction, and fixing SPUTargetLowering::computeMaskedBitsFor-
TargetNode().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50462 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-30 00:30:08 +00:00
Anton Korobeynikov
966e7997b5
Don't do stupid things: doInitialization(Module&) is not applicable to ModulePass :)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50433 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-29 18:16:22 +00:00