Commit Graph

107170 Commits

Author SHA1 Message Date
David Majnemer
0e4fc41b0d InstCombine: sub nsw %x, C -> add nsw %x, -C if C isn't INT_MIN
We can preserve nsw during this transform if -C won't overflow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216269 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-22 16:41:23 +00:00
Alex Lorenz
4ef54c3f85 [Support] Fix the overflow bug in ULEB128 decoding.
Differential Revision: http://reviews.llvm.org/D5029


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216268 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-22 16:29:45 +00:00
Sasa Stankovic
cc59c3f335 [mips] Don't use odd-numbered float registers for double arguments for fastcc
calling convention if FP is 64-bit and +nooddspreg is used.

Differential Revision: http://reviews.llvm.org/D4981.diff


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216262 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-22 09:23:22 +00:00
David Majnemer
c86bdc73e8 InstCombine: Don't unconditionally preserve 'nsw' when shrinking constants
Consider:
  %add = add nsw i32 %a, -16777216
  %and = and i32 %add, 255

Regardless of whether or not we demand the sign bit of %add, we cannot
replace -16777216 with 2130706432 without also removing 'nsw' from the
instruction.

This fixes PR20377.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216261 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-22 07:56:32 +00:00
Erik Eckstein
6ca2d8b7c7 fix: SLPVectorizer crashes for unreachable blocks containing not schedulable instructions.
In unreachable blocks it's legal to have instructions like "%x = op %x".
Such instuctions are not schedulable. Therefore the SLPVectorizer has to check for
unreachable blocks and ignore them.

Fixes bug 20646.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216256 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-22 01:18:39 +00:00
Peter Collingbourne
f5377021c5 [dfsan] Fix non-determinism bug in non-zero label check annotator.
We now use a std::vector instead of a DenseSet to store the list of
label checks so that we can iterate over it deterministically.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216255 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-22 01:18:18 +00:00
David Majnemer
54056f1760 ValueTracking: Figure out more bits when looking at add/sub
Given something like X01XX + X01XX, we know that the result must look
like X1XXX.

Adapted from a patch by Richard Smith, test-case written by me.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216250 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-22 00:40:43 +00:00
Reid Kleckner
2c0e02e21b SROA: Handle a case of store size being smaller than allocation size
In this case, we are creating an x86_fp80 slice for a union from C where
the padding bytes may contain real data. An x86_fp80 alloca is 16 bytes,
and that's just fine. We can't, however, use regular loads and stores to
access the slice, because the store size is only 10 bytes / 80 bits.
Instead, use memcpy and memset.

Fixes PR18726.

Reviewed By: chandlerc

Differential Revision: http://reviews.llvm.org/D5012

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216248 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-22 00:09:56 +00:00
Duncan P. N. Exon Smith
5e83e81ab2 Revert "X86: Align the stack on word boundaries in LowerFormalArguments()"
This (mostly) reverts commit r216119.

Somewhere during the review Reid committed r214980 which fixed this
another way, and I neglected to check that the testcase still failed
before committing.

I've left test/CodeGen/X86/aligned-variadic.ll around in case it adds
extra coverage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216246 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 23:36:08 +00:00
Reid Kleckner
a79efd7469 Add an explicit move constructor to SrcBuffer
MSVC can't synthesize the explicit one.  Instead it tries to emit a copy
ctor which would call the deleted copy ctor of unique_ptr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216244 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 23:24:08 +00:00
Juergen Ributzka
5e34dffb9c [FastISel][AArch64] Add support for variable shift.
This adds the missing variable shift support for value type i8, i16, and i32.

This fixes <rdar://problem/18095685>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216242 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 23:06:07 +00:00
Philip Reames
daebbe217e Minor refactor to make applying patches from 'Add a "probe-stack" attribute' review thread out of order easier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216241 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 22:53:49 +00:00
David Blaikie
c7260209a8 Use DILexicalBlockFile, rather than DILexicalBlock, to track discriminator changes to ensure discriminator changes don't introduce new DWARF DW_TAG_lexical_blocks.
Somewhat unnoticed in the original implementation of discriminators, but
it could cause instructions to end up in new, small,
DW_TAG_lexical_blocks due to the use of DILexicalBlock to track
discriminator changes.

Instead, use DILexicalBlockFile which we already use to track file
changes without introducing new scopes, so it works well to track
discriminator changes in the same way.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216239 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 22:45:21 +00:00
Sanjay Patel
d1a09c47d2 name change: isPow2DivCheap -> isPow2SDivCheap
isPow2DivCheap

That name doesn't specify signed or unsigned.

Lazy as I am, I eventually read the function and variable comments. It turns out that this is strictly about signed div. But I discovered that the comments are wrong:

   srl/add/sra

is not the general sequence for signed integer division by power-of-2. We need one more 'sra':

   sra/srl/add/sra

That's the sequence produced in DAGCombiner. The first 'sra' may be removed when dividing by exactly '2', but that's a special case.

This patch corrects the comments, changes the name of the flag bit, and changes the name of the accessor methods.

No functional change intended.

Differential Revision: http://reviews.llvm.org/D5010


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216237 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 22:31:48 +00:00
Quentin Colombet
bd66db27fd [PeepholeOptimizer] Enable the advanced copy optimization by default.
The advanced copy optimization does not yield any difference on the whole llvm
test-suite + SPECs, either in compile time or runtime (binaries are identical),
but has a big potential when data go back and forth between register files as
demonstrated with test/CodeGen/ARM/adv-copy-opt.ll.

Note: This was measured for both Os and O3 for armv7s, arm64, and x86_64.

<rdar://problem/12702965>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216236 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 22:23:52 +00:00
Philip Reames
9bdd5df2ca Whitespace change to reduce diff in future patch.
Patch 2 of 11 in 'Add a "probe-stack" attribute' review thread

Patch by: john.kare.alsaker@gmail.com



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216235 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 22:19:16 +00:00
Philip Reames
ecad452885 [X86] Split out the logic to select the stack probe function (NFC)
Patch 1 of 11 in 'Add a "probe-stack" attribute' review thread.

Patch by: <john.kare.alsaker@gmail.com>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216233 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 22:15:20 +00:00
Robin Morisset
a204592582 Add hooks for emitLeading/TrailingFence
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216232 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 22:09:25 +00:00
Robin Morisset
cf165c36ee Rename AtomicExpandLoadLinked into AtomicExpand
AtomicExpandLoadLinked is currently rather ARM-specific. This patch is the first of
a group that aim at making it more target-independent. See
http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-August/075873.html
for details

The command line option is "atomic-expand"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216231 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 21:50:01 +00:00
Quentin Colombet
4921d1af7d [PeepholeOptimizer] Update the kill flags when extending the live-range of the
source of a copy.

<rdar://problem/12702965>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216229 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 21:34:06 +00:00
Justin Bogner
6d2164ec3d Fix a URL (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216228 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 21:09:24 +00:00
Juergen Ributzka
5d6365c80c [FastISel][AArch64] Use the correct register class to make the MI verifier happy.
This is mostly achieved by providing the correct register class manually,
because getRegClassFor always returns the GPR*AllRegClass for MVT::i32 and
MVT::i64.

Also cleanup the code to use the FastEmitInst_* method whenever possible. This
makes sure that the operands' register class is properly constrained. For all
the remaining cases this adds the missing constrainOperandRegClass calls for
each operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216225 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 20:57:57 +00:00
David Blaikie
95ca0fb247 Explicitly pass ownership of the MemoryBuffer to AddNewSourceBuffer using std::unique_ptr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216223 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 20:44:56 +00:00
Tom Stellard
fdbf61d00d R600/SI: Teach moveToVALU how to handle more S_LOAD_* instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216220 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 20:41:00 +00:00
Tom Stellard
5f52739370 R600/SI: Make sure SCRATCH_WAVE_OFFSET is added as Live-In to the function
This fixes a crash in an ocl conformance test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216219 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 20:40:58 +00:00
Tom Stellard
7af96a25fc R600/SI: Remove unused SGPR spilling code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216218 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 20:40:56 +00:00
Tom Stellard
9b60cb102a R600/SI: Use eliminateFrameIndex() to expand SGPR spill pseudos
This will simplify the SGPR spilling and also allow us to use
MachineFrameInfo for calculating offsets, which should be more
reliable than our custom code.

This fixes a crash in some cases where a register would be spilled
in a branch such that the VGPR defined for spilling did not dominate
all the uses when restoring.

This fixes a crash in an ocl conformance test.  The test requries
register spilling and is too big to include.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216217 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 20:40:54 +00:00
Tom Stellard
a07c0778ca R600/SI: Handle VCC in SIRegisterInfo::getPhysRegSubReg()
This fixes a crash in an ocl conformance test.  The test requries
register spilling and is too big to include.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216216 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 20:40:50 +00:00
Rafael Espindola
3fd7e37b34 Rewrite the gold plugin to fix pr19901.
There is a fundamental difference between how the gold API and lib/LTO view
the LTO process.

The gold API talks about a particular symbol in a particular file. The lib/LTO
API talks about a symbol in the merged module.

The merged module is then defined in terms of the IR semantics. In particular,
a linkonce_odr GV is only copied if it is used, since it is valid to drop
unused linkonce_odr GVs.

In the testcase in pr19901 both properties collide. What happens is that gold
asks us to keep a particular linkonce_odr symbol, but the IR linker doesn't
copy it to the merged module and we never have a chance to ask lib/LTO to keep
it.

This patch fixes it by having a more direct implementation of the gold API. If
it asks us to keep a symbol, we change the linkage so it is not linkonce. If it
says we can drop a symbol, we do so. All of this before we even send the module
to lib/Linker.

Since now we don't have to produce LTO_SYMBOL_SCOPE_DEFAULT_CAN_BE_HIDDEN,
during symbol resolution we can use a temporary LLVMContext and do lazy
module loading. This allows us to keep the minimum possible amount of
allocated memory around. This should also allow as much parallelism as
we want, since there is no shared context.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216215 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 20:28:55 +00:00
Jonathan Roelofs
96c909cc74 Satiate the sanitizer build bot
This fixes a missing initializer from r216182


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216212 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 20:09:15 +00:00
Rafael Espindola
7b4eb02b6d Move some logic to populateLTOPassManager.
This will avoid code duplication in the next commit which calls it directly
from the gold plugin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216211 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 20:03:44 +00:00
Adam Nemet
9db660ecaa [AVX512] Add class to group common template arguments related to vector type
We discussed the issue of generality vs. readability of the AVX512 classes
recently.  I proposed this approach to try to hide and centralize the mappings
we commonly perform based on the vector type.  A new class X86VectorVTInfo
captures these.

The idea is to pass an instance of this class to classes/multiclasses instead
of the corresponding ValueType.  Then the class/multiclass can use its field
for things that derive from the type rather than passing all those as separate
arguments.

I modified avx512_valign to demonstrate this new approach.  As you can see
instead of 7 related template parameters we now have one.  The downside is
that we have to refer to fields for the derived values.  I named the argument
'_' in order to make this as invisible as possible.  Please let me know if you
absolutely hate this.  (Also once we allow local initializations in
multiclasses we can recover the original version by assigning the fields to
local variables.)

Another possible use-case for this class is to directly map things, e.g.:

  RegisterClass KRC = X86VectorVTInfo<32, i16>.KRC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216209 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 19:50:07 +00:00
Alex Lorenz
93695d2395 Coverage Mapping: add function's hash to coverage function records.
The profile data format was recently updated and the new indexing api
requires the code coverage tool to know the function's hash as well
as the function's name to get the execution counts for a function.

Differential Revision: http://reviews.llvm.org/D4994


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216207 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 19:23:25 +00:00
Rafael Espindola
9ca2a9ae4e llvm-gcc is dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216206 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 19:22:24 +00:00
Eric Fiselier
29863d8e18 [LIT] Remove documentation for method since it does not exist
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216204 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 18:52:58 +00:00
Rafael Espindola
4658ea9dc7 Respect LibraryInfo in populateLTOPassManager and use it. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216203 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 18:49:52 +00:00
Rafael Espindola
8d1b742f7f Remove dead code. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216201 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 18:11:21 +00:00
Quentin Colombet
ad3c6289b6 [AArch64] Run a peephole pass right after AdvSIMD pass.
The AdvSIMD pass may produce copies that are not coalescer-friendly. The
peephole optimizer knows how to fix that as demonstrated in the test case.

<rdar://problem/12702965>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216200 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 18:10:07 +00:00
Juergen Ributzka
60aadd5d8b [FastISel][AArch64] Factor out ANDWri instruction generation into a helper function. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216199 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 18:02:25 +00:00
Moritz Roth
a6afad8b33 Thumb1 load/store optimizer: Improve code to materialize new base register.
There are two add-immediate instructions in Thumb1: tADDi8 and tADDi3. Only
the latter supports using different source and destination registers, so
whenever we materialize a new base register (at a certain offset) we'd do
so by moving the base register value to the new register and then adding in
place. This patch changes the code to use a single tADDi3 if the offset is
small enough to fit in 3 bits.

Differential Revision: http://reviews.llvm.org/D5006

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216193 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 17:11:03 +00:00
Hans Wennborg
eeb828f029 Use returns_nonnull in BumpPtrAllocator and MallocAllocator to avoid null-check in placement new
In both Clang and LLVM, this is a common pattern:

  Size = sizeof(DeclRefExpr) + SomeExtraStuff;
  void *Mem = Context.Allocate(Size, llvm::alignOf<DeclRefExpr>());
  return new (Mem) DeclRefExpr(...);

The annoying thing is that because the default placement-new operator has a
nothrow specification, the compiler will insert a null check of Mem before
calling the DeclRefExpr constructor. This null check is redundant for us,
because we expect the allocation functions to never return null.

By annotating the allocator functions with returns_nonnull, we can optimize
away these checks. Compiling clang with a recent version of Clang and measuring
with:

  $ perf stat -r20 bin/clang.patch -fsyntax-only -w gcc.c && perf stat -r20 bin/clang.orig -fsyntax-only -w gcc.c

Shows a 2.4% speed-up (+- 0.8%).

The pattern occurs in LLVM too. Measuring with -O3 (and now using bzip2.c
instead, because it's smaller):

  $ perf stat -r20 bin/clang.patch -O3 -w bzip2.c  &&  perf stat -r20 bin/clang.orig -O3 -w bzip2.c

Shows 4.4 % speed-up (+- 1%).

If anyone knows of a similar attribute we can use for MSVC, or some other
technique to get rid off the null check there, please let me know.

Differential Revision: http://reviews.llvm.org/D4989

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216192 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 17:10:00 +00:00
Juergen Ributzka
69ec09b61f [FastISel][AArch64] Remove redundant test.
These tests and many more are already covered by fast-isel-addressing-modes.ll.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216186 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 16:40:05 +00:00
Jonathan Roelofs
4c3be1aa0f Add a thread-model knob for lowering atomics on baremetal & single threaded systems
http://reviews.llvm.org/D4984


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216182 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 14:35:47 +00:00
Rafael Espindola
0b994a70b0 Handle inlining in populateLTOPassManager like in populateModulePassManager.
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216178 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 13:35:30 +00:00
Zinovy Nis
63f5912959 [CLNUP] Remove return after llvm_unreachable. Thanks to Hal Finkel for pointing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216176 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 13:30:05 +00:00
Benjamin Kramer
daada81e5c DAGCombiner: Make concat_vector combine safe for EVTs and concat_vectors with many arguments.
PR20677

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216175 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 13:28:02 +00:00
Rafael Espindola
47199c3d0c Move DisableGVNLoadPRE from populateLTOPassManager to PassManagerBuilder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216174 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 13:13:17 +00:00
Josh Klontz
f19807db70 X86AsmPrinter MCJIT MSVC bug fix.
Summary:
This bug was introduced in r213006 which makes an assumption that MCSection is COFF for Windows MSVC. This assumption is broken for MCJIT users where ELF is used instead [1]. The fix is to change the MCSection cast to a dyn_cast.

[1] http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-December/068407.html.

Reviewers: majnemer

Reviewed By: majnemer

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D4872

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216173 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 12:55:27 +00:00
Oliver Stannard
760a46522a [ARM] Enable DP copy, load and store instructions for FPv4-SP
The FPv4-SP floating-point unit is generally referred to as
single-precision only, but it does have double-precision registers and
load, store and GPR<->DPR move instructions which operate on them.
This patch enables the use of these registers, the main advantage of
which is that we now comply with the AAPCS-VFP calling convention.
This partially reverts r209650, which added some AAPCS-VFP support,
but did not handle return values or alignment of double arguments in
registers.

This patch also adds tests for Thumb2 code generation for
floating-point instructions and intrinsics, which previously only
existed for ARM.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216172 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 12:50:31 +00:00
Rafael Espindola
fc4bdcdc87 Sort declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216171 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 12:39:07 +00:00