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Author SHA1 Message Date
Eric Christopher
100c833416 Have LowerOperandForConstraint handle multiple character constraints. 
Part of rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132510 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 23:16:42 +00:00
Jakob Stoklund Olesen
4f3fb6d08b Flag unallocatable register classes instead of giving them empty 
allocation orders.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132509 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 23:07:24 +00:00
Jakob Stoklund Olesen
f462e3fac7 Make it possible to have unallocatable register classes. 
Some register classes are only used for instruction operand constraints.
They should never be used for virtual registers. Previously, those
register classes were given an empty allocation order, but now you can
say 'let isAllocatable=0' in the register class definition.

TableGen calculates if a register is part of any allocatable register
class, and makes that information available in TargetRegisterDesc::inAllocatableClass.

The goal here is to eliminate use cases for overriding allocation_order_*
methods.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132508 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 23:07:20 +00:00
Devang Patel
d633089783 Preserve line number information while converting Invoke into a Call. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132505 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 22:46:58 +00:00
Bill Wendling
76dd0de6d5 This should have been a C++ testcase. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132504 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 22:26:15 +00:00
Jakob Stoklund Olesen
6edf90b8a7 Just use a SmallVector. 
I was confused whether new uint8_t[] would zero-initialize the returned
array, and it seems that so is gcc-4.0.

This should fix the test failures on darwin 9.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132500 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 22:22:43 +00:00
Bill Wendling
effc34ec59 Testcase for r132493. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132495 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 22:12:42 +00:00
Bill Wendling
7a6037c4e0 Update for r132493 change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132494 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 22:11:49 +00:00
Devang Patel
ee1f87881b Remove dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132488 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 21:31:00 +00:00
Devang Patel
e29e8e100e Update DBG_VALUEs while breaking anti dependencies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132487 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 21:26:52 +00:00
Tanya Lattner
201cfcd6de Fix encoding for VEXTdf. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132486 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 21:25:24 +00:00
Eli Friedman
70d893e84b PR10067: Add missing safety check to call return transformation in MemCpyOpt::processStore. If something accesses the dest of the "copy" between the call and the copy, the performCallSlotOptzn transformation is not valid. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132485 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 21:24:42 +00:00
Devang Patel
cf4cc84738 During post RA scheduling, do not try to chase reg defs. to preserve DBG_VALUEs. This approach has several downsides, for example, it does not work when dbg value is a constant integer, it does not work if reg is defined more than once, it places end of debug value range markers in the wrong place. It even causes misleading incorrect debug info when duplicate DBG_VALUE instructions point to same reg def. 
Instead, use simpler approach and let DBG_VALUE follow its predecessor instruction. After live debug value analysis pass, all DBG_VALUE instruction are placed at the right place. Thanks Jakob for the hint!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132483 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 20:07:12 +00:00
Rafael Espindola
580cbd9cf0 Add test for PR10068. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132482 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 20:02:48 +00:00
Rafael Espindola
251b4a0405 Revert 132424 to fix PR10068. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132479 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 19:57:47 +00:00
Stuart Hastings
552c0ee4f9 Andy pointed out a dumb omission in this test case. Thanks Andy! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132477 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 19:26:49 +00:00
Eric Christopher
5fab03d54c Add a new parse hint for multi-letter constraints in inline asm. 
Testcase will come when we use it.

Part of rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132476 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 19:26:37 +00:00
Stuart Hastings
1f344f052e Jakob pointed out a dumb omission in this test case. Thanks Jakob! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132472 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 18:44:05 +00:00
Jakob Stoklund Olesen
5d20c3152b Use RegisterClassInfo::getOrder in RAFast. 
This saves two virtual function calls and an Allocatable BitVector test,
making RAFast run 2% faster.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132471 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 18:35:30 +00:00
Jim Grosbach
6f888a80d5 .cfi directive register parsing flexibility. 
Parsing a register name/number for .cfi directives can't assume that a
register name starts with a '%' token. Be more flexible and check for a
register number instead. Still unlikely to be perfect, but it allows us
to parse both plain identifiers as register names and integers as register
numbers, which is what we're wanting to support at this point.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132466 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 17:14:04 +00:00
Stuart Hastings
84be958ed8 Omit unnecessary stack copy when x87 input is a load. 
rdar://problem/6373334


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132458 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 15:57:11 +00:00
Benjamin Kramer
19e1f633af Start with a zeroed CSRNum map. 
Found by valgrind.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132457 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 12:07:44 +00:00
Jakob Stoklund Olesen
ab5ceacbc1 Initialize members to fix problem found by valgrind. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132456 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 05:43:49 +00:00
Jakob Stoklund Olesen
fa226bccaa Use TRI::has{Sub,Super}ClassEq() where possible. 
No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132455 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 05:43:46 +00:00
Stuart Hastings
ac92565384 Tweak testcase for ARM bot. rdar://problem/5993888 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132454 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 05:05:39 +00:00
Rafael Espindola
cde4ce411b Don't hardcode the %reg format in the streamer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132451 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 02:34:55 +00:00
Jakob Stoklund Olesen
491a13691d Add a RegisterClassInfo class that lazily caches information about 
register classes.

It provides information for each register class that cannot be
determined statically, like:

- The number of allocatable registers in a class after filtering out the
  reserved and invalid registers.

- The preferred allocation order with registers that overlap callee-saved
  registers last.

- The last callee-saved register that overlaps a given physical register.

This information usually doesn't change between functions, so it is
reused for compiling multiple functions when possible.  The many
possible combinations of reserved and callee saves registers makes it
unfeasible to compute this information statically in TableGen.

Use RegisterClassInfo to count available registers in various heuristics
in SimpleRegisterCoalescing, making the pass run 4% faster.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132450 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 02:19:35 +00:00
Akira Hatanaka
5e06903e66 Detect FI|cst pattern in MipsDAGToDAGISel::SelectAddr. Patch by Sasa Stankovic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132448 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 01:03:14 +00:00
Akira Hatanaka
f876bf81df Test case for r132444. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132445 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 00:25:53 +00:00
Akira Hatanaka
2e591477af Custom-lower FRAMEADDR. Patch by Sasa Stankovic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132444 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 00:24:44 +00:00
Eli Friedman
7c6a5a2c39 When marking a block as being unanalyzable, use "Clobber" on the terminator instead of the first instruction in the block. This is a bit of a hack; "Clobber" isn't really the right marking in the first place. memdep doesn't really have any way of properly expressing "unanalyzable" at the moment. Using it on the terminator is much less ambiguous than using it on an arbitrary instruction, though. 
In the given testcase, the "Clobber" was pointing to a load, and GVN was incorrectly assuming that meant that the "Clobber" load overlapped the load being analyzed (when they are actually unrelated).

The included testcase tests both this commit and r132434.

Part two of rdar://9429882.  (r132434 was mislabeled.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132442 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 00:08:52 +00:00
Chad Rosier
11772e093f Typos. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132437 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 23:32:40 +00:00
Eli Friedman
fc09797426 In MemoryDependenceAnalysis::getNonLocalPointerDepFromBB, if a given block is is deemed unanalyzable (and we execute one of the "goto PredTranslationFailure" statements), make sure we don't put information about the predecessors of that block into the returned data structures; this can lead to, among other things, extraneous results (which will confuse passes using memdep). Fixes an assert in GVN compiling ruby. Part of rdar://problem/9521954 . 
Testcase coming up soon.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132434 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 23:16:53 +00:00
Devang Patel
4ada1d7910 A DBG_VALUE that truncates a range does not start another dbg value range. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132433 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 23:00:17 +00:00
Devang Patel
c432907eca Do not drop constant values when a variable's content is described using .debug_loc entries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132427 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 22:03:25 +00:00
Stuart Hastings
ec880283b3 Recommit 132404 with fixes. rdar://problem/5993888 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132424 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 21:33:14 +00:00
Eric Christopher
9aaa02a1d2 Allow bitcasts between valid types of the same size and vector 
types if the vector type is legal.

Fixes rdar://9306086


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132420 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 19:55:10 +00:00
Stuart Hastings
4abc5fea9c Revert 132404 to appease a buildbot. rdar://problem/5993888 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132419 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 19:52:20 +00:00
Nadav Rotem
96e0c5477c Refactor LegalizeTypes: Erase LegalizeAction and make the type legalizer use 
the TargetLowering enum.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132418 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 19:47:10 +00:00
Andrew Trick
cf31f91931 SCEV: missing null check fix for r132360, dragonegg crash. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132416 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 19:14:56 +00:00
Jakob Stoklund Olesen
76395c9a31 Revert r132358 "Simplify the eviction policy by making the failsafe explicit." 
This commit caused regressions in i386 flops-[568], matrix, salsa20,
256.bzip2, and enc-md5.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132413 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 18:45:02 +00:00
Stuart Hastings
090bf19de6 Fix double FGETSIGN to work on x86_32; followup to 132396. 
rdar://problem/5660695


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132411 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 18:32:25 +00:00
Eric Christopher
a3d91cd6a6 Add a testcase, enabled only on arm, for llvm-gcc r132366. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132409 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 18:23:56 +00:00
Stuart Hastings
0f971b1fdb Cleanup test case. rdar://problem/5660695 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132408 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 18:23:14 +00:00
Benjamin Kramer
0be9f5dde4 Initialize IssueWidth to zero. 
Fixes valgrind errors in the CellSPU backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132405 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 17:19:08 +00:00
Stuart Hastings
10ff0bbdfb Add support for x86 CMPEQSS and friends. These instructions do a 
floating-point comparison, generate a mask of 0s or 1s, and generally
DTRT with NaNs.  Only profitable when the user wants a materialized 0
or 1 at runtime.  rdar://problem/5993888


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132404 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 17:17:45 +00:00
Stuart Hastings
f1002828fd Reapply 132348 with fixes. rdar://problem/6501862 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132402 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 16:42:47 +00:00
Stuart Hastings
d7de954644 A forthcoming SSE patch will break this test; since the test is also 
valid for x87, re-target to x87.  rdar://problem/5993888


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132401 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 16:13:09 +00:00
Stuart Hastings
b909d35de4 Test case for 132396. rdar://problem/5660695 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132399 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 15:50:29 +00:00
Jakob Stoklund Olesen
1f9a09c614 Fix PR10059 and future variations by handling all register subclasses. 
Add TargetRegisterInfo::hasSubClassEq and use it to check for compatible
register classes instead of trying to list all register classes in
X86's getLoadStoreRegOpcode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132398 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 15:32:10 +00:00