This will be used to replace things like X86's MOV32to32_.
Enhance ScheduleDAGSDNodesEmit to be more flexible and robust
in the presense of subregister superclasses and subclasses. It
can now cope with the definition of a virtual register being in
a subclass of a use.
Re-introduce the code for recording register superreg classes and
subreg classes. This is needed because when subreg extracts and
inserts get coalesced away, the virtual registers are left in
the correct subclass.
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in multiple classes in the case that the classes are all
in subset/superset relations. This function is used by the
fast-isel emitter, which always wants the super-most set.
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Note that these are distinct from TargetInstrInfo::INSERT_SUBREG
and TargetInstrInfo::EXTRACT_SUBREG, which are used.
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register classes. Before, MVT::Other would be returned anytime a reg was
in multiple register classes. Now, MVT::Other is only returned if the types
for those register classes differ.
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- Make type declarations match the struct/class keyword of the definition.
- Move AddSignalHandler into the namespace where it belongs.
- Correctly call functions from template base.
- Some other small changes.
With this patch, LLVM and Clang should build properly and with far less noise under VS2008.
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in selectiondag patterns. This is required for the upcoming shuffle_vector rewrite,
and as it turns out, cleans up a hack in the Alpha instruction info.
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This allows tblgen to handle include "foo.td" when the quote is exactly
the last character in a file. rdar://6695728
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component's warnings to process for '-gen-clang-diags-defs'.
Also, when the component is specified, generate a '#if' prologue at the top of
the generated .def file (to match the current files).
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tablegen files to the original .def preprocessor include files. This is my first
TableGen backend; I don't claim that it is awesome.
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errors when thrown. This gets us nice errors like this from tblgen:
CMOVL32rr: (set GR32:i32:$dst, (X86cmov GR32:$src1, GR32:$src2))
/Users/sabre/llvm/Debug/bin/tblgen: error:
Included from X86.td:116:
Parsing X86InstrInfo.td:922: In CMOVL32rr: X86cmov node requires exactly 4 operands!
def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
^
instead of just:
CMOVL32rr: (set GR32:i32:$dst, (X86cmov GR32:$src1, GR32:$src2))
/Users/sabre/llvm/Debug/bin/tblgen: In CMOVL32rr: X86cmov node requires exactly 4 operands!
This is all I plan to do with this, but it should be easy enough to improve if anyone
cares (e.g. keeping more loc info in "dag" expr records in tblgen.
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refers to the "prefix" directory, i.e., one level above "bin". LLVMGCCPATH
is used as the directory containing the llvm-gcc executable, so add a "/bin"
suffix to get from LLVMGCCDIR to LLVMGCCPATH.
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linkage: this linkage type only applies to declarations,
but ODR is only relevant to globals with definitions.
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and extern_weak_odr. These are the same as the non-odr versions,
except that they indicate that the global will only be overridden
by an *equivalent* global. In C, a function with weak linkage can
be overridden by a function which behaves completely differently.
This means that IP passes have to skip weak functions, since any
deductions made from the function definition might be wrong, since
the definition could be replaced by something completely different
at link time. This is not allowed in C++, thanks to the ODR
(One-Definition-Rule): if a function is replaced by another at
link-time, then the new function must be the same as the original
function. If a language knows that a function or other global can
only be overridden by an equivalent global, it can give it the
weak_odr linkage type, and the optimizers will understand that it
is alright to make deductions based on the function body. The
code generators on the other hand map weak and weak_odr linkage
to the same thing.
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them are generic changes.
- Use the "fast" flag that's already being passed into the asm printers instead
of shoving it into the DwarfWriter.
- Instead of calling "MI->getParent()->getParent()" for every MI, set the
machine function when calling "runOnMachineFunction" in the asm printers.
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a DBG_LABEL or not. We want to fall back to the original way of emitting debug
info when we're in -O0/-fast mode.
- Add plumbing in to pass the "Fast" flag to places that need it.
- XFAIL DebugInfo/deaddebuglabel.ll. This is finding 11 labels instead of 8. I
need to investigate still.
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* Linters now return their information instead of printing it, to
enable easier unittesting
* Added support for finding tabs in files, added to C++ linter
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function. Emitting another label after the prologue messes up the debugging. We
are doing that because the first DebugLoc object it sees is different from the
previous, which was nothing. Check for this situation, and don't emit one if
it's the first.
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Cleanup some warning.
Remark: when struct/class are declared differently than they are defined, this make problem for VC++ since it seems to mangle class differently that struct. These error are very hard to understand and find. So please, try to keep your definition/declaration in sync.
Only tested with VS2008. hope it does not break anything. feel free to revert.
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target directories themselves. This also means that VMCore no longer
needs to know about every target's list of intrinsics. Future work
will include converting the PowerPC target to this interface as an
example implementation.
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crashes or wrong code with codegen of large integers:
eliminate the legacy getIntegerVTBitMask and
getIntegerVTSignBit methods, which returned their
value as a uint64_t, so couldn't handle huge types.
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- Modify TableGen to add the DebugLoc when calling getTargetNode.
(The light-weight wrappers are only temporary. The non-DebugLoc version will be
removed once the whole debug info stuff is finished with.)
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after the code that sorts the patterns. This doesn't
affect the output, but it makes the code a little easier
to follow.
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to handle LLVMMatchType intrinsic parameters, and by adding new subclasses
of LLVMMatchType to match vector types with integral elements that are
either twice as wide or half as wide as the elements of the matched type.
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- After GlobalAssign, emit addrspace before global/constant, to follow
the new syntax.
- Eliminate "type void", which is now invalid.
- Fix invalid liblists like [, "foo"].
- Tweak whitespace in a few places.
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- Add several new keywords
- Clean up some obsolete keywords
- Improve the patterns for constants.
- Add syntax-highlighting for dejagnu test command comments
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smarter about C-ish syntax, and supports the cinoptions
variable. Set cinoptions to suppress the extra indentation
for switch case labels.
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* Fixed cursors in terminal by setting nocompatible (sorry, vi users)
* Enable syntax highlighting so that this file can stand on its own
* Highlight trailing whitespace
* Fixed commands to delete trailing whitespaces and convert tabs to spaces
llvm.vim and tablegen.vim
* Removed trailing whitespace, as it's now very visible
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* Added the first LLVM unittest -- DenseMap.
* Updated mkpatch utility to include llvm/unittests dir
* Added top-level target "unittests" to run all unittests
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* Removed gtest_main.cc: we have our own main() elsewhere
* Simplified the Makefile as we don't need SOURCES
* Moved the internal header to gtest/internal/
* Simplified the Makefile to remove -I param to CPP.Flags
* Updated README.LLVM with all the steps I took to massage GTest to
work in LLVM so far
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Makefile with it, without resorting to the use of VPATH.
Also added Makefiles at every level of the directory tree to properly recurse
to Google Test and build it as a library (original Makefiles by Talin).
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Added a README.LLVM file to indicate which files and directories
were removed from the original source tarball.
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This would be much easier to do if the CommandLine library didn't use
global state. Global state is evil.
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for(Type1 B = ...;;) { Type2 B ; ... }
is bad: code is hard to read and VS VS don't like it (it ignore the second declaration of B).
This patch fix the problem in tablegen. Please don't write code like this.
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foldMemoryOperand how to "fold" them, by converting them into constant-pool
loads. When they aren't folded, they use xorps/cmpeqd, but for example when
register pressure is high, they may now be folded as memory operands, which
reduces register pressure.
Also, mark V_SET0 isAsCheapAsAMove so that two-address-elimination will
remat it instead of copying zeros around (V_SETALLONES was already marked).
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is set but mayLoad is not set. Fix all the problems this turned up.
Change code to not use isSimpleLoad instead of mayLoad unless it
really wants isSimpleLoad.
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