Commit Graph

676 Commits

Author SHA1 Message Date
Chris Lattner
a6dc9fb745 Fix a bug handling instructions, like blr, which just consist of a text
string.  The return value of printInstruction should be true for these.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29196 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-19 01:39:06 +00:00
Evan Cheng
e6f32034db Add code size to target instruction use it as the 3rd isel sorting tie-breaker.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29193 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-19 00:24:41 +00:00
Evan Cheng
6f6602ce42 Make sub- super- reg-class tables static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29190 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-18 22:18:31 +00:00
Chris Lattner
195bb4a7b0 Fix case where identical cases were not detected across case #0, because
instructions not handled would have a case value of #0, throwing things off.
This marginally shrinks the X86 asmprinter, but shrinks the sparc asmwriter
by 25 lines.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29187 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-18 19:27:30 +00:00
Chris Lattner
0a01212857 Fix an accidentally duplicated line that caused tblgen to crash on itanium.
Add an assert that catches the real problem earlier.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29185 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-18 19:06:01 +00:00
Chris Lattner
96c1ade5c3 Maximally group commands. When all instructions within a command set have a
series of identical commands, handle them all with one switch.  In the case
of the x86 at&t asm printer, only 3 switches are needed for all instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29184 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-18 18:28:27 +00:00
Chris Lattner
b84628679a Change generator to remove operands as it processes them. No change in
generated file.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29183 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-18 17:56:07 +00:00
Chris Lattner
191dd1f186 Handle the last operand more intelligently. When emitting the \n, also
return from the asmprinter to make the generated asmprinter both more
efficient and smaller.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29182 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-18 17:50:22 +00:00
Chris Lattner
e7a589df09 Emit switches with 1/2 cases as unconditional code or an if/then/else for
tidyness.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29181 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-18 17:43:54 +00:00
Chris Lattner
b51ecd4dd9 Steal bits from the asm string index to use for operand information. On both
x86 and ppc, this gets us 4 more bits to play with, since the string indices
both only use 12 bits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29180 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-18 17:38:46 +00:00
Chris Lattner
5561640043 Merge operand info and asmstr idx into a single 32-bit field. No other change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29179 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-18 17:32:27 +00:00
Chris Lattner
bdff5f95b9 Completely change the structure of the generated asmprinter to be more table
based and less switch-statements-with-hundreds-of-cases based.  This shrinks
the x86 asmprinters to about 1/3 their previous size.

Other improvements coming.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29177 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-18 17:18:03 +00:00
Evan Cheng
fb878a37ba Use __attribute__((noinline)) only if compiled by gcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29161 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-16 06:14:37 +00:00
Evan Cheng
f872940dfc Parameterize target node ValueType to allow more sharing of emit functions.
Also reduce the number of arguments passed to emit functions and removed a
hack.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29160 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-16 06:12:52 +00:00
Evan Cheng
fceb57a917 Reduce instruction selection code size and stack frame size by factoring
code that emit target specific nodes into emit functions that are uniquified
and shared among selection routines.
e.g. This reduces X86ISelDAGToDAG.o (release) from ~2M to ~1.5M. Stack frame
size of Select_store from ~13k down to ~8k.
This is the first step. Further work to enable more sharing will follow.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29158 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-15 08:45:20 +00:00
Chris Lattner
fb5115e84c The generated index array should be const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29155 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-14 23:14:02 +00:00
Chris Lattner
6af022f255 Emit the string information for the asm writer as a single large string
and index into it, instead of emitting it like this:

  static const char * const OpStrs[] = {
    "PHINODE\n",        // PHI
    0,  // INLINEASM
    "adc ",     // ADC32mi
    "adc ",     // ADC32mi8
   ...

The old way required thousands of relocations that slows down link time and
dynamic load times.

This also cuts about 10K off each of the X86 asmprinters, and should shrink
the others as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29152 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-14 22:59:11 +00:00
Jim Laskey
cb12903147 Clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29137 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-13 22:17:08 +00:00
Jim Laskey
f1b05bf755 1. Simplfy bit operations.
2. Coalesce instruction cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29135 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-13 21:02:53 +00:00
Jim Laskey
ed393433d2 Move base value of instruction to lookup table to prepare for case reduction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29122 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-12 19:15:43 +00:00
Jim Laskey
16d42c6ac6 It was pointed out that DEBUG() is only available with -debug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29106 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-11 18:25:13 +00:00
Jim Laskey
e37fe9b3a1 Ensure that dump calls that are associated with asserts are removed from
non-debug build.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29105 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-11 17:58:07 +00:00
Jim Laskey
1406bdab85 Reduce bloat in target libraries by removing per machine instruction assertion
from code emitter generation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29097 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-11 01:25:59 +00:00
Chris Lattner
a539c03271 tblgen uses EH
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29034 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-07 00:21:17 +00:00
Evan Cheng
322812e603 Ugly hack! Add helper functions InsertInFlightSetEntry and
RemoveInFlightSetEntry. They are used in place of direct set operators to
reduce instruction selection function stack size.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28987 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-29 23:57:05 +00:00
Chris Lattner
02cdb377ec Fix an error message regression. Print:
LI8:    (LI8:i64 (imm:i64):$imm)
instead of:
  LI8:    (LI8:MVT::i64 (imm:MVT::i64):$imm)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28868 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-20 00:56:37 +00:00
Chris Lattner
186fb7d131 Don't require src/dst patterns to be able to fully resolve their types,
because information about one can help refine the other.  This allows us to
write:

def : Pat<(i32 (extload xaddr:$src, i8)),
          (LBZX xaddr:$src)>;

as:

def : Pat<(extload xaddr:$src, i8),
          (LBZX xaddr:$src)>;

because tblgen knows LBZX returns i32.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28865 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-20 00:31:27 +00:00
Chris Lattner
a354849c27 Make sure to use the result of the pattern to infer the result type of the
instruction, and the result type of the instruction to refine the pattern.
This allows us to write things like this:

def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;

as:
def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (VR128:$src)>

and fixes a ppc64 issue.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28863 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-20 00:18:02 +00:00
Chris Lattner
8f60d54fb1 Improve a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28833 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-16 18:25:06 +00:00
Evan Cheng
8d3af5e7d0 Instructions with variable operands (variable_ops) can have a number required
operands. e.g.
def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
                "call {*}$dst", [(X86call GR32:$dst)]>;
TableGen should emit operand informations for the "required" operands.

Added a target instruction info flag M_VARIABLE_OPS to indicate the target
instruction may have more operands in addition to the minimum required
operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28791 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-15 07:22:16 +00:00
Evan Cheng
d7c2c86239 Allow more use of iPTR in patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28790 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-15 00:16:37 +00:00
Evan Cheng
e945f4d3d4 Added support for variable_ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28788 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-14 22:22:20 +00:00
Evan Cheng
bc6b86a89e Fix support for optional input flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28784 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-14 19:27:50 +00:00
Evan Cheng
50c997e26a getOperandNum(): error if specified operand number is out of range.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28775 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-13 21:47:27 +00:00
Chris Lattner
11bcd28dff Wrap to 80 cols
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28743 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-09 23:59:44 +00:00
Reid Spencer
d386e55e33 Don't build tblgen with -pedantic or -Wno-long-long
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28638 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-01 18:20:23 +00:00
Evan Cheng
553ef1be94 Can't trust NodeDepth when checking for possibility of load folding creating
a cycle. This increase the search space and will increase compile time (in
practice it appears to be small, e.g. 176.gcc goes from 62 sec to 65 sec)
that will be addressed later.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28476 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-25 20:16:55 +00:00
Evan Cheng
b0793f9741 Fixed a really ugly bug. The TableGen'd isel is not freeing the "inflight set"
correctly. That is causing non-deterministic behavior (and possibly preventing
some load folding from happening).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28458 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-25 00:21:44 +00:00
Chris Lattner
243be2c80d Don't make zero-sized static arrays
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28448 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-24 17:31:02 +00:00
Chris Lattner
d74ea2bbd8 Patches to make the LLVM sources more -pedantic clean. Patch provided
by Anton Korobeynikov!  This is a step towards closing PR786.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28447 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-24 17:04:05 +00:00
Evan Cheng
d15531b430 Now that iPTR is a fully resolved type. We end up losing the type check for
patterns that look like this:

def : Pat<(i32 (X86Wrapper tconstpool  :$dst)), (MOV32ri tconstpool  :$dst)>;

InsertOneTypeCheck should copy the type from the resolved pattern to the
unresolved one as long as there types are different.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28389 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-19 07:24:32 +00:00
Evan Cheng
21d03f2de0 lib/Target/Target.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28386 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-18 20:42:07 +00:00
Evan Cheng
764811f145 Don't generate getCalleeSaveReg and getCalleeSaveRegClasses anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28376 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-18 00:08:46 +00:00
Evan Cheng
6b12516f1a Typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28366 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-17 20:55:51 +00:00
Evan Cheng
2618d07765 Remove PointerType from target definition. Use abstract type MVT::iPTR to
represent pointer type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28363 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-17 20:37:59 +00:00
Evan Cheng
44a65fa552 Allow patterns to refer to physical registers that belong to multiple
register classes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28323 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-16 07:05:30 +00:00
Evan Cheng
9812f1ca97 Noop instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28241 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-12 07:47:00 +00:00
Evan Cheng
d9d4518a86 Unused instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28240 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-12 07:42:01 +00:00
Evan Cheng
2ca0efd71a Also add super- register classes info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28221 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-11 07:30:26 +00:00
Evan Cheng
3eff89bf89 Watch out for the following case:
1. Use expects a chain output.
2. Node is expanded into multiple target ops.
3. One of the inner node produces a chain, the outer most one doesn't.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28209 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-10 02:47:57 +00:00