6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-09 10:29:21 +00:00
Code Issues Projects Releases Wiki Activity
33,359 Commits 39 Branches 0 Tags 277 MiB
11ce02dbdd
Commit Graph

322 Commits

Author SHA1 Message Date
Dan Gohman
70fb1aefd5 Fix a bug in the folding of binary operators to undef. 
Thanks to Lauro for spotting this!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38491 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-10 15:19:29 +00:00
Dan Gohman
d595b5f1f0 Fix the folding of undef in several binary operators to recognize 
undef in either the left or right operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38489 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-10 14:20:37 +00:00
Dan Gohman
d6fd1bc122 Preserve volatililty and alignment information when lowering or 
simplifying loads and stores.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38473 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-09 22:18:38 +00:00
Chris Lattner
e094f54f4c Fix this warning: 
DAGCombiner.cpp: In member function 'llvm::SDOperand<unnamed>::DAGCombiner::visitOR(llvm::SDNode*)':
DAGCombiner.cpp:1608: warning: passing negative value '-0x00000000000000001' for argument 1 to 'llvm::SDOperand llvm::SelectionDAG::getConstant(uint64_t, llvm::MVT::ValueType, bool)'

oiy.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38458 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-09 16:16:34 +00:00
Dan Gohman
613e0d8008 Fix several over-aggressive folds for undef nodes in dagcombine, to 
follow the rules for undef used in instcombine.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37851 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-03 14:03:57 +00:00
Dan Gohman
23ff1826b9 Teach GetNegatedExpression to negate 0-B to B in UnsafeFPMath mode, and 
visitFSUB to fold 0-B to -B in UnsafeFPMath mode. Also change visitFNEG
to use isNegatibleForFree/GetNegatedExpression instead of doing a subset
of the same thing manually.

This fixes test/CodeGen/X86/negative-sin.ll.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37842 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-02 15:48:56 +00:00
Dan Gohman
7f32156bb9 Generalize MVT::ValueType and associated functions to be able to represent 
extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.

This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37719 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-25 16:23:39 +00:00
Dan Gohman
ea859be53c Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from 
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37704 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-22 14:59:07 +00:00
Evan Cheng
b13cdbd865 Xforms: 
(add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
(sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37685 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-21 07:39:16 +00:00
Dan Gohman
b5bec2b6f6 Pass a SelectionDAG into SDNode::dump everywhere it's used, in prepration 
for needing the DAG node to print pre-legalize extended value types, and
to get better debug messages with target-specific nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37656 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-19 14:13:56 +00:00
Dan Gohman
51eaa86758 Rename MVT::getVectorBaseType to MVT::getVectorElementType. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37579 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-14 22:58:02 +00:00
Chris Lattner
3adf951364 tighten up recursion depth again 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37330 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-25 02:19:06 +00:00
Evan Cheng
c843abe868 Fix a typo that caused combiner to create mal-formed pre-indexed store where value store is the same as the base pointer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37318 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-24 02:35:39 +00:00
Chris Lattner
501fee71e0 prevent exponential recursion in isNegatibleForFree 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37310 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-23 07:35:22 +00:00
Dan Gohman
fcc4dd91e5 Qualify calls to getTypeForValueType with MVT:: too. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37233 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-18 18:41:29 +00:00
Dale Johannesen
98a6c62aff Don't fold bitconvert(load) for preinc/postdec loads. Likewise stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37130 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 22:45:30 +00:00
Chris Lattner
c76d4410ab Use a ptr set instead of a linear search to unique TokenFactor operands. 
This fixes PR1423


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37102 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 06:37:59 +00:00
Evan Cheng
93003b8cf2 Bug fix: should check ABI alignment, not pref. alignment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37094 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 02:04:50 +00:00
Lauro Ramos Venancio
b5bb7ffa9c Fix an infinite recursion in GetNegatedExpression. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37086 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-15 17:05:43 +00:00
Chris Lattner
2944652569 implement a simple fneg optimization/propagation thing. This compiles: 
CodeGen/PowerPC/fneg.ll into:

_t4:
        fmul f0, f3, f4
        fmadd f1, f1, f2, f0
        blr

instead of:

_t4:
        fneg f0, f3
        fmul f0, f0, f4
        fmsub f1, f1, f2, f0
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37054 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-14 22:04:50 +00:00
Evan Cheng
2c4f94363a Can't fold the bit_convert is the store is a truncating store. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36962 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-09 21:49:47 +00:00
Evan Cheng
c2cd2b29f5 Forgot a check. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36910 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-07 21:36:06 +00:00
Evan Cheng
59d5b68dff Enable a couple of xforms: 
- (store (bitconvert v)) -> (store v) if resultant store does not require
higher alignment
- (bitconvert (load v)) -> (load (bitconvert*)v) if resultant load does not
require higher alignment


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36908 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-07 21:27:48 +00:00
Evan Cheng
a7d4a04d24 Don't create indexed load / store with zero offset! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36716 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-03 23:52:19 +00:00
Evan Cheng
498f55989a Forgot about chain result; also UNDEF cannot have multiple values. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36622 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-01 08:53:39 +00:00
Evan Cheng
45a7ca9b23 * Only turn a load to UNDEF if all of its outputs have no uses (indexed loads 
produce two results.)
* Do not touch volatile loads.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36604 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-01 00:38:21 +00:00
Christopher Lamb
95c218a83e PR400 phase 2. Propagate attributed load/store information through DAGs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36356 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-22 23:15:30 +00:00
Reid Spencer
c67bdc288a Revert Christopher Lamb's load/store alignment changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36309 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-21 18:36:27 +00:00
Christopher Lamb
2330e4d4c4 add support for alignment attributes on load/store instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36301 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-21 08:16:25 +00:00
Chris Lattner
61a4c072b9 allow SRL to simplify its operands, as it doesn't demand all bits as input. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36245 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-18 03:06:49 +00:00
Chris Lattner
ec06e9a670 When replacing a node in SimplifyDemandedBits, if the old node used any 
single-use nodes, they will be dead soon.  Make sure to remove them before
processing other nodes.  This implements CodeGen/X86/shl_elim.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36244 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-18 03:05:22 +00:00
Chris Lattner
95a5e0507e SIGN_EXTEND_INREG does not demand its top bits. Give SimplifyDemandedBits 
a chance to hack on it.  This compiles:

int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }

into:
_baz:
        slwi r2, r3, 8
        srwi r2, r2, 9
        extsh r3, r2
        blr

instead of:

_baz:
        srwi r2, r4, 24
        rlwimi r2, r3, 8, 0, 23
        srwi r2, r2, 9
        extsh r3, r2
        blr

This implements CodeGen/PowerPC/sign_ext_inreg1.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36212 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-17 19:03:21 +00:00
Chris Lattner
c24bbaddf8 fix an infinite loop compiling ldecod, notice by JeffC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35910 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-11 16:51:53 +00:00
Chris Lattner
1eba01e9a0 Fix this harder. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35888 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-11 06:50:51 +00:00
Chris Lattner
c56a81dff1 don't create shifts by zero, fix some problems with my previous patch 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35887 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-11 06:43:25 +00:00
Chris Lattner
20a35c3fa5 Teach the codegen to turn [aez]ext (setcc) -> selectcc of 1/0, which often 
allows other simplifications.  For example, this compiles:
int isnegative(unsigned int X) {
   return !(X < 2147483648U);
}

Into this code:

x86:
        movl 4(%esp), %eax
        shrl $31, %eax
        ret
arm:
        mov r0, r0, lsr #31
        bx lr
thumb:
        lsr r0, r0, #31
        bx lr

instead of:

x86:
        cmpl $0, 4(%esp)
        sets %al
        movzbl %al, %eax
        ret

arm:
        mov r3, #0
        cmp r0, #0
        movlt r3, #1
        mov r0, r3
        bx lr

thumb:
        mov r2, #1
        mov r1, #0
        cmp r0, #0
        blt LBB1_2      @entry
LBB1_1: @entry
        cpy r2, r1
LBB1_2: @entry
        cpy r0, r2
        bx lr

Testcase here: test/CodeGen/Generic/ispositive.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35883 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-11 05:32:27 +00:00
Chris Lattner
1982ef20c4 Codegen integer abs more efficiently using the trick from the PPC CWG. This 
improves codegen on many architectures.  Tests committed as CodeGen/*/iabs.ll

X86 Old:			X86 New:
_test:				_test:
   movl 4(%esp), %ecx		   movl 4(%esp), %eax
   movl %ecx, %eax		   movl %eax, %ecx
   negl %eax			   sarl $31, %ecx
   testl %ecx, %ecx		   addl %ecx, %eax
   cmovns %ecx, %eax		   xorl %ecx, %eax
   ret				   ret

PPC Old:			PPC New:
_test:				_test:
   cmpwi cr0, r3, -1		   srawi r2, r3, 31
   neg r2, r3			   add r3, r3, r2
   bgt cr0, LBB1_2 ;		   xor r3, r3, r2
LBB1_1: ;			   blr
   mr r3, r2
LBB1_2: ;
   blr

ARM Old:			ARM New:
_test:				_test:
   rsb r3, r0, #0		   add r3, r0, r0, asr #31
   cmp r0, #0			   eor r0, r3, r0, asr #31
   movge r3, r0			   bx lr
   mov r0, r3
   bx lr

Thumb Old:			Thumb New:
_test:				_test:
   neg r2, r0			   asr r2, r0, #31
   cmp r0, #0			   add r0, r0, r2
   bge LBB1_2			   eor r0, r2
LBB1_1: @			   bx lr
   cpy r0, r2
LBB1_2: @
   bx lr


Sparc Old:			Sparc New:
test:				test:
   save -96, %o6, %o6		   save -96, %o6, %o6
   sethi 0, %l0			   sra %i0, 31, %l0
   sub %l0, %i0, %l0		   add %i0, %l0, %l1
   subcc %i0, -1, %l1		   xor %l1, %l0, %i0
   bg .BB1_2			   restore %g0, %g0, %g0
   nop				   retl
.BB1_1:				   nop
   or %g0, %l0, %i0
.BB1_2:
   restore %g0, %g0, %g0
   retl
   nop

It also helps alpha/ia64 :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35881 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-11 05:11:38 +00:00
Scott Michel
c9dc114578 1. Insert custom lowering hooks for ISD::ROTR and ISD::ROTL. 
2. Help DAGCombiner recognize zero/sign/any-extended versions of ROTR and ROTL
patterns. This was motivated by the X86/rotate.ll testcase, which should now
generate code for other platforms (and soon-to-come platforms.) Rewrote code
slightly to make it easier to read.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35605 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-02 21:36:32 +00:00
Dale Johannesen
2041a0ef75 Fix incorrect combination of different loads. Reenable zext-over-truncate 
combination.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35517 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-30 21:38:07 +00:00
Evan Cheng
b0b6c76ffe Disable load width reduction xform of variant (zext (truncate load x)) for 
big endian targets until llvm-gcc build issue has been resolved.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35449 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-29 07:56:46 +00:00
Evan Cheng
15213b77cf SIGN_EXTEND_INREG requires one extra operand, a ValueType node. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35350 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-26 07:12:51 +00:00
Evan Cheng
dae54ce7fc Adjust offset to compensate for big endian machines. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35293 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-24 00:02:43 +00:00
Evan Cheng
e177e307fc Make sure SEXTLOAD of the specific type is supported on the target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35289 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-23 22:13:36 +00:00
Evan Cheng
b37b80ce46 Also replace uses of SRL if that's also folded during ReduceLoadWidth(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35286 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-23 20:55:21 +00:00
Evan Cheng
0b063def98 A couple of bug fixes for reducing load width xform: 
1. Address offset is in bytes.
2. Make sure truncate node uses are replaced with new load.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35274 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-23 02:16:52 +00:00
Evan Cheng
c88138fb5e More opportunities to reduce load size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35254 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-22 01:54:19 +00:00
Evan Cheng
007b69eeaa fold (truncate (srl (load x), c)) -> (smaller load (x+c/vt bits)) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35239 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-21 20:14:05 +00:00
Evan Cheng
83060c544b Avoid combining indexed load further. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35005 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-07 08:07:03 +00:00
Chris Lattner
b654176cb4 fold away addc nodes when we know there cannot be a carry-out. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34913 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-04 20:40:38 +00:00
Chris Lattner
bcf2484450 generalize 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34910 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-04 20:08:45 +00:00