Commit Graph

90345 Commits

Author SHA1 Message Date
Andrew Trick
1754aca83a MachineModel: Add a ProcResGroup class.
This allows abitrary groups of processor resources. Using something in
a subset automatically counts againts the superset. Currently, this
only works if the superset is also a ProcResGroup as opposed to a
SuperUnit.

This allows SandyBridge to be expressed naturally, which will be
checked in shortly.

def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>;
def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>;
def SBPort23  : ProcResGroup<[SBPort2, SBPort3]>;
def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>;

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177112 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 21:21:50 +00:00
Hal Finkel
0cc52c67db Move estimateStackSize from ARM into MachineFrameInfo
This is a generic function (derived from PEI); moving it into
MachineFrameInfo eliminates a current redundancy between the ARM and AArch64
backends, and will allow it to be used by the PowerPC target code.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177111 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 21:15:20 +00:00
Hal Finkel
3080d23fde Provide the register scavenger to processFunctionBeforeFrameFinalized
Add the current PEI register scavenger as a parameter to the
processFunctionBeforeFrameFinalized callback.

This change is necessary in order to allow the PowerPC target code to
set the register scavenger frame index after the save-area offset
adjustments performed by processFunctionBeforeFrameFinalized. Only
after these adjustments have been made is it possible to estimate
the size of the stack frame.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177108 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 20:33:40 +00:00
Hal Finkel
1c6c61a608 Use frame-index scavenging for PPC register spilling
Make requiresFrameIndexScavenging return true, and create virtual registers in
the spilling code instead of using the register scavenger directly. This makes
the target-level code simpler, and importantly, delays the scavenging until
after callee-saved register processing (which will be important for later
changes).

Also cleans up trackLivenessAfterRegAlloc (makes it inline in the header with
the other related functions). This makes it clear that it always returns true.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177107 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 20:21:47 +00:00
Hal Finkel
100a94bc93 Not all PPC functions with a frame pointer need a RS spill slot
We used to add a spill slot for the register scavenger whenever the function
has a frame pointer. This is unnecessarily conservative: We may need the spill
slot for dynamic stack allocations, and functions with dynamic stack
allocations always have a FP, but we might also have a FP for other reasons
(such as the user explicitly disabling frame-pointer elimination), and we don't
necessarily need a spill slot for those functions.

The structsinregs test needed adjustment because it disables FP elimination.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177106 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 19:34:32 +00:00
Arnold Schwaighofer
d81511f0a6 ARM cost model: Increase cost of some vector selects we do terrible on
By terrible I mean we store/load from the stack.

This matters on PAQp8 in _Z5trainPsS_ii (which is inlined into Mixer::update)
where we decide to vectorize a loop with a VF of 8 resulting in a 25%
degradation on a cortex-a8.

LV: Found an estimated cost of 2 for VF 8 For instruction:   icmp slt i32
LV: Found an estimated cost of 2 for VF 8 For instruction:   select i1, i32, i32

The bug that tracks the CodeGen part is PR14868.

radar://13403975

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177105 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 19:17:02 +00:00
Akira Hatanaka
042b79625f [mips] Fix filename in comment and delete unnecessary lines of code.
No functionality changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177104 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 19:09:52 +00:00
Jyotsna Verma
cec50e6da2 Hexagon: Removed asserts regarding alignment and offset.
We are warning the user about the alignment, so we should not assert.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177103 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 19:08:03 +00:00
Arnold Schwaighofer
e2188d9c43 Add missing asserts flag to test - it uses debug flags
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177102 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 19:01:58 +00:00
Akira Hatanaka
21eecf4384 Android uses cacheflush(long start, long end, long flags) for MIPS.
Patch by Stephen Hines.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177101 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 19:01:00 +00:00
Arnold Schwaighofer
d517da33b7 LoopVectorize: Invert case when we use a vector cmp value to query select cost
We generate a select with a vectorized condition argument when the condition is
NOT loop invariant. Not the other way around.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177098 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 18:54:36 +00:00
Akira Hatanaka
862146b607 Add back lines which were accidentally deleted in CMakeLists.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177096 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 18:46:46 +00:00
Akira Hatanaka
275f354d6d [mips] Define function MipsSEDAGToDAGISel::selectAddESubE.
No intended functionality changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177095 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 18:39:25 +00:00
Hal Finkel
6bc99603c0 Add a comment about overlapping PPC frame offsets
I don't think that it is otherwise clear how the overlapping offsets
are processed into distinct spill slots. Comment that this is done
in processFunctionBeforeFrameFinalized.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177094 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 18:38:31 +00:00
Akira Hatanaka
f283512d72 [mips] Rename functions and variables to start with proper case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177092 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 18:33:23 +00:00
Akira Hatanaka
1d905668dd Add header file MipsISelDAGToDAG.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177090 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 18:28:19 +00:00
Akira Hatanaka
554d9312b2 [mips] Define two subclasses of MipsDAGToDAGISel. Mips16DAGToDAGISel is for
mips16 and MipsSEDAGToDAGISel is for mips32/64. 

No functionality changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177089 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 18:27:31 +00:00
Shuxin Yang
a0c9939873 Perform factorization as a last resort of unsafe fadd/fsub simplification.
Rules include:
  1)1 x*y +/- x*z => x*(y +/- z) 
    (the order of operands dosen't matter)

  2) y/x +/- z/x => (y +/- z)/x 

 The transformation is disabled if the new add/sub expr "y +/- z" is a 
denormal/naz/inifinity.

rdar://12911472


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177088 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 18:08:26 +00:00
Adrian Prantl
d9e90b20e2 Test that we emit a DW_AT_location for self captured by a block.
This is the backend part of a CFE test with the same name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177087 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 17:54:13 +00:00
Vincent Lejeune
3ab0ba3cd8 R600: Factorize code handling Const Read Port limitation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177078 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 15:50:45 +00:00
Alexey Samsonov
b4ba5e68e1 [ASan] emit instrumentation for initialization order checking by default
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177063 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 12:38:58 +00:00
Chandler Carruth
41b55f5556 PR14972: SROA vs. GVN exposed a really bad bug in SROA.
The fundamental problem is that SROA didn't allow for overly wide loads
where the bits past the end of the alloca were masked away and the load
was sufficiently aligned to ensure there is no risk of page fault, or
other trapping behavior. With such widened loads, SROA would delete the
load entirely rather than clamping it to the size of the alloca in order
to allow mem2reg to fire. This was exposed by a test case that neatly
arranged for GVN to run first, widening certain loads, followed by an
inline step, and then SROA which miscompiles the code. However, I see no
reason why this hasn't been plaguing us in other contexts. It seems
deeply broken.

Diagnosing all of the above took all of 10 minutes of debugging. The
really annoying aspect is that fixing this completely breaks the pass.
;] There was an implicit reliance on the fact that no loads or stores
extended past the alloca once we decided to rewrite them in the final
stage of SROA. This was used to encode information about whether the
loads and stores had been split across multiple partitions of the
original alloca. That required threading explicit tracking of whether
a *use* of a partition is split across multiple partitions.

Once that was done, another problem arose: we allowed splitting of
integer loads and stores iff they were loads and stores to the entire
alloca. This is a really arbitrary limitation, and splitting at least
some integer loads and stores is crucial to maximize promotion
opportunities. My first attempt was to start removing the restriction
entirely, but currently that does Very Bad Things by causing *many*
common alloca patterns to be fully decomposed into i8 operations and
lots of or-ing together to produce larger integers on demand. The code
bloat is terrifying. That is still the right end-goal, but substantial
work must be done to either merge partitions or ensure that small i8
values are eagerly merged in some other pass. Sadly, figuring all this
out took essentially all the time and effort here.

So the end result is that we allow splitting only when the load or store
at least covers the alloca. That ensures widened loads and stores don't
hurt SROA, and that we don't rampantly decompose operations more than we
have previously.

All of this was already fairly well tested, and so I've just updated the
tests to cover the wide load behavior. I can add a test that crafts the
pass ordering magic which caused the original PR, but that seems really
brittle and to provide little benefit. The fundamental problem is that
widened loads should Just Work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177055 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 11:32:24 +00:00
Joerg Sonnenberger
4bf030402d Add two of the float related ARM-specific entries for e_flags needed for
linkers to interact with GNU ld.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177016 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 08:01:36 +00:00
Craig Topper
fdf168fbc4 Fix the name of a variable to match its declaration. Fixes build failure from r177014.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177015 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 07:47:43 +00:00
Craig Topper
9d3f3c5f40 Fix a bug in the calculation of the VEX.B bit for FMA4 rr with the VEX.W bit set. The VEX.B was being calculated from the wrong operand. Fixes at least some portion of PR14185.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177014 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 07:40:52 +00:00
Craig Topper
599521f167 Teach X86 MC instruction lowering that VMOVAPSrr and other VEX-encoded register to register moves should be switched from using the MRMSrcReg form to the MRMDestReg form if the source register is a 64-bit extended register and the destination register is not. This allows the instruction to be encoded using the 2-byte VEX form instead of the 3-byte VEX form. The GNU assembler has similar behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177011 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 07:09:57 +00:00
Michael Liao
6f8c6852a0 Fix PR15309
- Fix the typo on type checking



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177010 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 06:57:42 +00:00
Jiong Wang
a3493e2ad8 test commit: remove blank line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177009 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 05:43:59 +00:00
Nick Lewycky
3804c750b4 Remove a change to the debug info in this test, that I made while testing
something else and forgot to remove.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177007 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 05:28:10 +00:00
Nick Lewycky
45d65858b0 Try using %S to find the emitted .gcno file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177006 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 05:23:30 +00:00
Nick Lewycky
347e88bb22 Remove accidentally committed debug line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177005 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 05:19:12 +00:00
Nick Lewycky
a204ef3168 Refactor GCOV's six constructor arguments into a struct with a getter that
constructs default arguments. It can now take default arguments from
cl::opt'ions. Add a new -default-gcov-version=... option, and actually test it!

Sink the reverse-order of the version into GCOVProfiling, hiding it from our
users.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177002 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 05:13:26 +00:00
Nick Lewycky
c14f1c4587 Fix typo in comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176997 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 01:26:17 +00:00
Michael J. Spencer
d483d2813c [Support][Test] Missed this in the API change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176996 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 00:33:37 +00:00
Michael J. Spencer
cc3a595ab9 [Support] Fix lifetime of file descriptors when using MemoryBuffer.
Clients of MemoryBuffer::getOpenFile expect it not to take ownership of the file
descriptor passed in. So don't.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176995 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 00:20:10 +00:00
Nick Lewycky
64a0a33307 No functionality change. Rename emitGCNO() to the more sensible
emitProfileNotes(), similar to emitProfileArcs(). Also update its comment.

Also add a comment on Version[4] (there will be another comment in clang later),
and compress lines that exceeded 80 columns.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176994 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13 22:55:42 +00:00
David Blaikie
22063d60ab Simplify file/directory name handling in DILexicalBlock
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176993 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13 22:52:59 +00:00
David Blaikie
036af14866 Remove an extra operand to a DIFile metadata entry
(extra cleanup/fallout from r176983 - not sure why I didn't catch this locally)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176988 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13 22:33:09 +00:00
Bill Wendling
4cb1f5f406 Reset some of the target options which affect code generation.
This doesn't reset all of the target options within the TargetOptions
object. This is because some of those are ABI-specific and must be determined if
it's okay to change those on the fly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176986 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13 22:26:59 +00:00
David Blaikie
33905b2a34 Simplify directory name handling in DILexicalBlockFile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176984 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13 22:23:51 +00:00
David Blaikie
e0805a992d Remove the unused 4th operand for DIFile debug info metadata
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176983 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13 22:05:21 +00:00
Lang Hames
a991b254f7 Make LTO codegen use a PassManager, rather than a FunctionPassManager, for the
codegen passes. This brings it in to line with clang and llc's codegen setup,
and tidies up the code.

If I understand correctly, adding ModulePasses to a FunctionPassManager is
bogus. It only seems to explode if an added ModulePass depends on a
FunctionPass though, which might be why this code has survived so long.

Fixes <rdar://problem/13386816>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176977 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13 21:18:46 +00:00
Alexey Samsonov
b91ce4fd9b Simplify CMake rules in HandleLLVMOptions module.
Summary: No functionality change.

Reviewers: Bigcheese

Reviewed By: Bigcheese

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D535

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176973 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13 20:50:23 +00:00
Reed Kotler
9106f73246 Add some additonal attribute helper functions. Test will be on follow
up putback to clang for mips16.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176968 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13 20:20:08 +00:00
Vincent Lejeune
321aded623 R600: Remove unused Outputs variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176967 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13 20:13:25 +00:00
Manman Ren
4c6f895205 No functionality change. Use unreachable in getCUOffset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176963 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13 18:41:27 +00:00
Manman Ren
b1e052aa1b No functionality change. Use unreachable in getCompileUnit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176962 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13 18:33:41 +00:00
Jakob Stoklund Olesen
e8a3cc6878 Check register classes also when changing them.
We have the same assertion in createVirtualRegister.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176959 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13 18:11:17 +00:00
Arnold Schwaighofer
d8bfde0c6a ARM cost model: Add test case to make sure we would notice a change in CodeGen
In r176898 I updated the cost model to reflect the fact that sext/zext/cast on
v8i32 <-> v8i8 and v16i32 <-> v16i8 are expensive.

This test case is so that we make sure to update the cost model once we fix
CodeGen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176955 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13 16:25:55 +00:00
Arnaud A. de Grandmaison
bdd2d98139 Fix a performance regression when combining to smaller types in icmp (shl %v, C1), C2 :
Only combine when the shl is only used by the icmp

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176950 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13 14:40:37 +00:00