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Author SHA1 Message Date
Jakob Stoklund Olesen
5fcb81dace Insert code in the right location when lowering PowerPC atomics. 
This causes defs to dominate uses, no instructions after terminators, and other
goodness.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128836 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-04 17:57:29 +00:00
Bruno Cardoso Lopes
ac79e4c82f - Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT 
also fix the encoding of the later.
- Add a new encoding bit to describe the index mode used in AM3.
- Teach printAddrMode3Operand to check by the addressing mode which
  index mode to print.
- Testcases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128832 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-04 17:18:19 +00:00
Akira Hatanaka
f49fde2877 Move transformation of JmpLink and related nodes done during instruction selection to Legalize phase. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128830 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-04 17:11:07 +00:00
Jakob Stoklund Olesen
cf3a74824f PowerPC atomic pseudos clobber CR0, they don't read it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128829 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-04 17:07:09 +00:00
Jakob Stoklund Olesen
2684c5db84 Use X0 instead of R0 for the zero register on ppc64. 
The 32-bit R0 cannot be used where a 64-bit register is expected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128828 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-04 17:07:06 +00:00
Joerg Sonnenberger
4a8ac8de1d Add support for the VIA PadLock instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128826 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-04 16:58:13 +00:00
Joerg Sonnenberger
229e4523f2 Expand Op0Mask by one bit in preparation for the PadLock prefixes. 
Define most shift masks incrementally to reduce the redundant
hard-coding. Introduce new shift for the VEX flags to replace the
magic constant 32 in various places.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128822 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-04 15:58:30 +00:00
Jay Foad
3e2f74e6d6 Remove some support for ReturnInsts with multiple operands, and for 
returning a scalar value in a function whose return type is a single-
element structure or array.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128810 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-04 07:44:02 +00:00
Che-Liang Chiou
357be5e4ae ptx: support setp's 4-operand format 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128767 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-02 08:51:39 +00:00
Cameron Zwarich
4071a71112 Do some peephole optimizations to remove pointless VMOVs from Neon to integer 
registers that arise from argument shuffling with the soft float ABI. These
instructions are particularly slow on Cortex A8. This fixes one half of
<rdar://problem/8674845>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128759 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-02 02:40:43 +00:00
Johnny Chen
04187ecd57 Fixed a bug in disassembly of STR_POST, where the immediate is the second operand in am2offset; 
instead of the second operand in addrmode_imm12.

rdar://problem/9225289


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128757 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-02 02:24:54 +00:00
Akira Hatanaka
ad8ffad60a Undo changes mistakenly made in revision 128750. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128751 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-02 00:26:12 +00:00
Akira Hatanaka
dc1652fd31 Insert space before ';' to prevent warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128750 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-02 00:15:58 +00:00
Johnny Chen
103bf951a4 Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000. 
rdar://problem/9224276


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128749 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 23:30:25 +00:00
Johnny Chen
6da3fe68c6 MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is UNPREDICTABLE. 
rdar://problem/9224120


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128748 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 23:15:50 +00:00
Johnny Chen
857b1939da Fix the instruction table entries for AI1_adde_sube_s_irs multiclass definition so that 
all the instruction have:

    let Inst{31-27} = 0b1110; // non-predicated

Before, the ARM decoder was confusing:

> 0x40 0xf3 0xb8 0x80

as:

Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------

	adcs	pc, r8, r0, asr #6

since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'.

Now, the AR decoder behaves correctly:

> 0x40 0xf3 0xb8 0x80
> END
Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt

Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------

	adcshi	pc, r8, r0, asr #6
> 

rdar://problem/9223094


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128746 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 22:32:51 +00:00
Evan Cheng
0539c159fb Avoid de-referencing pass beginning of a basic block. No small test case possible. rdar://9216009 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128743 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 22:09:28 +00:00
Akira Hatanaka
ad8180a0b8 Remove redundant code. There are assignments to variables Base and Offset right after the code that is removed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128742 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 21:56:02 +00:00
Akira Hatanaka
e2e436a6bc Simplifies logic for printing target flags. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128741 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 21:41:06 +00:00
Owen Anderson
1721324d97 When the architecture is explicitly armv6 or thumbv6, we need to mark the object file appropriately. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128739 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 21:07:39 +00:00
Jim Grosbach
9a3507f091 LDRD/STRD instructions should print both Rt and Rt2 in the asm string. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128736 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 20:26:57 +00:00
Johnny Chen
ec30f6f5e5 Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction 
as invalid.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128734 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 20:21:38 +00:00
Akira Hatanaka
a4485c4964 Modifies MipsAsmPrinter::isBlockOnlyReachableByFallthrough so that it handles delay slots correctly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128724 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 18:57:38 +00:00
Johnny Chen
5307da994a Fix LDRi12 immediate operand, which was changed to be the second operand in $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm). 
rdar://problem/9219356


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128722 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 18:26:38 +00:00
Akira Hatanaka
20ada98de8 Add code for analyzing FP branches. Clean up branch Analysis functions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128718 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 17:39:08 +00:00
Benjamin Kramer
0e3ee43ea0 Initialize HasVMLxForwarding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128709 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 09:20:31 +00:00
Evan Cheng
8e23e815ad Issue libcalls __udivmod*i4 / __divmod*i4 for div / rem pairs. 
rdar://8911343


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128696 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 00:42:02 +00:00
Matt Beaumont-Gay
e3662cca5d Remove unused variables 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128692 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 00:06:01 +00:00
Bruno Cardoso Lopes
ae0855401b Apply again changes to support ARM memory asm parsing. I removed 
all LDR/STR changes and left them to a future patch. Passing all
checks now.

- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
  fix the encoding wherever is possible.
- Add a new encoding bit to describe the index mode used and teach
  printAddrMode2Operand to check by the addressing mode which index
  mode to print.
- Testcases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128689 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 23:26:08 +00:00
Jakob Stoklund Olesen
1db952d0c6 Provide a legal pointer register class when targeting thumb1. 
The LocalStackSlotAllocation pass was creating illegal registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128687 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 23:02:15 +00:00
Evan Cheng
463d358f1d Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplier 
accumulator forwarding:
vadd d3, d0, d1
vmul d3, d3, d2
=>
vmul d3, d0, d2
vmla d3, d1, d2


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128665 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 19:38:48 +00:00
Johnny Chen
a52d7da1d8 Fix single word and unsigned byte data transfer instruction encodings so that 
Inst{4} = 0.

rdar://problem/9213022


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128662 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 19:28:35 +00:00
Akira Hatanaka
1d6b38d9d3 Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128650 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 18:26:17 +00:00
Johnny Chen
8901e6ff3d Add BLXi to the instruction table for disassembly purpose. 
A8.6.23 BLX (immediate)

rdar://problem/9212921


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128644 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 17:53:50 +00:00
Bruno Cardoso Lopes
b41aaab5a1 Revert r128632 again, until I figure out what break the tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128635 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 15:54:36 +00:00
Richard Osborne
e8f3533323 Add XCore intrinsics for initializing / starting / synchronizing threads. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128633 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 15:13:13 +00:00
Bruno Cardoso Lopes
bcd3a9cd84 Reapply r128585 without generating a lib depedency cycle. An updated log: 
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
  {STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible.
- Move all instructions which use am2offset without a pattern to use
  addrmode2.
- Add a new encoding bit to describe the index mode used and teach
  printAddrMode2Operand to check by the addressing mode which index
  mode to print.
- Testcases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128632 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 14:52:28 +00:00
Matt Beaumont-Gay
e4345c9977 Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and" 
This revision introduced a dependency cycle, as nlewycky mentioned by email.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128597 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 00:39:16 +00:00
Owen Anderson
6a7d36a320 Somehow we managed to forget to encode the lane index for a large swathe of NEON instructions. With this fix, the entire test-suite passes with the Thumb integrated assembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128587 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-30 23:45:29 +00:00
Evan Cheng
ee2e0e347e Don't try to create zero-sized stack objects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128586 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-30 23:44:13 +00:00
Bruno Cardoso Lopes
40829ed6f5 - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and 
{STR,LDC}{2}_PRE.
- Fixed the encoding in some places.
- Some of those instructions were using am2offset and now use addrmode2.
Codegen isn't affected, instructions which use SelectAddrMode2Offset were not
touched.
- Teach printAddrMode2Operand to check by the addressing mode which index
mode to print.
- This is a work in progress, more work to come. The idea is to change places
which use am2offset to use addrmode2 instead, as to unify assembly parser.
- Add testcases for assembly parser

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128585 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-30 23:32:32 +00:00
Cameron Zwarich
c0e6d780cd Add a ARM-specific SD node for VBSL so that forms with a constant first operand 
can be recognized. This fixes <rdar://problem/9183078>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128584 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-30 23:01:21 +00:00
Akira Hatanaka
81bd78b897 fixed typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128574 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-30 21:15:35 +00:00
Jay Foad
3ecfc861b4 Remove PHINode::reserveOperandSpace(). Instead, add a parameter to 
PHINode::Create() giving the (known or expected) number of operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128537 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-30 11:28:46 +00:00
Evan Cheng
92e3916c3b Add intrinsics @llvm.arm.neon.vmulls and @llvm.arm.neon.vmullu.* back. Frontends 
was lowering them to sext / uxt + mul instructions. Unfortunately the
optimization passes may hoist the extensions out of the loop and separate them.
When that happens, the long multiplication instructions can be broken into
several scalar instructions, causing significant performance issue.

Note the vmla and vmls intrinsics are not added back. Frontend will codegen them
as intrinsics vmull* + add / sub. Also note the isel optimizations for catching
mul + sext / zext are not changed either.

First part of rdar://8832507, rdar://9203134


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128502 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-29 23:06:19 +00:00
Cameron Zwarich
3007d3331b Add Neon SINT_TO_FP and UINT_TO_FP lowering from v4i16 to v4f32. Fixes 
<rdar://problem/8875309> and <rdar://problem/9057191>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128492 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-29 21:41:55 +00:00
Owen Anderson
d0cfc99b30 Check early if this is an unsupported opcode, so that we can avoid needlessly instantiating the base register in some cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128481 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-29 20:27:38 +00:00
Johnny Chen
9eda569a74 A8.6.188 STC, STC2 
The STC_OPTION and STC2_OPTION instructions should have their coprocessor option enclosed in {}.

rdar://problem/9200661


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128478 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-29 19:49:38 +00:00
Owen Anderson
9eae80051b Add safety check that didn't show up in testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128467 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-29 17:42:25 +00:00
Owen Anderson
848b0c39b1 Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually exist. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128461 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-29 16:45:53 +00:00