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Author SHA1 Message Date
Rafael Espindola
6688c4a742 Fix PR8313 by changing ValueToValueMap use a TrackingVH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116390 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 02:08:17 +00:00
Evan Cheng
14ce175216 Limit load / store issues (at least until we have a true multi-issue aware scheduler). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116389 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 01:54:21 +00:00
Rafael Espindola
1ed219a9d2 Be more consistent in using ValueToValueMapTy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116387 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 01:36:30 +00:00
Bill Wendling
6932643a37 Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test 
just yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116386 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 01:17:33 +00:00
Bill Wendling
54908dd72b Add encodings for VCVT instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116385 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 00:56:35 +00:00
Jim Grosbach
89c898f8af Add ARM encoding information for comparisons, forced-cc-out arithmetics, and 
arithmetic-with-carry-in instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116384 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 00:50:27 +00:00
Bill Wendling
1fc6d8837f Add VCMPZ and VABS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116383 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 00:38:07 +00:00
Tobias Grosser
67be08a2f1 RegionInfo: Free the RegionNodes in cache. 
Contributed by: ether

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116380 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 00:07:59 +00:00
Bill Wendling
cd77686254 Refactor VCMP instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116379 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 00:04:29 +00:00
Jim Grosbach
ef324d7044 Add the rest of the ARM so_reg encoding options (register shifted register) 
and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116377 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:53:58 +00:00
Eric Christopher
8f9145b0eb FileCheckize this in a hope to quiet a valgrind warning on grep. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116376 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:47:58 +00:00
Bill Wendling
5a1fd8cf68 Add encodings for VNMUL[SD]. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116375 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:47:37 +00:00
Bill Wendling
caa3d467ab Add encodings for VDIV and VMUL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116370 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:22:27 +00:00
Evan Cheng
3f490f3469 Turn some fp stackifier assertion into errors to avoid silently generating bad code when assertions are off. rdar://8540457. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116368 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:19:28 +00:00
Jim Grosbach
2a6a93d542 Move the ARM so_imm encoding into a custom operand encoder and remove the 
explicit handling of the instructions referencing it from the MC code
emitter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116367 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:18:08 +00:00
Jim Grosbach
c14b80f6d3 Be nitpicky and line up the comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116365 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:14:03 +00:00
Bill Wendling
52061f83e7 Refactor some of the encoding logic into a base class. This keeps us from having 
to add 10+ lines to every instruction.

It may turn out that we can move this base class into it's parent class.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116362 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:06:54 +00:00
Jim Grosbach
08bd54987f Add custom encoder for the 's' bit denoting whether an ARM arithmetic 
instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116360 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:00:24 +00:00
Bill Wendling
dd3bc112e6 Add encoding for VSUB and VCMP. 
Fear not! I'm going to try a refactoring right now. :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116359 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 22:55:35 +00:00
Bill Wendling
6e8bf26342 Don't need to specify calling convention. Add 'readnone' to functions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116354 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 22:24:10 +00:00
Jim Grosbach
5013f7469e Allow targets to optionally specify custom binary encoder functions for 
operand values. This is useful for operands which require additional trickery
to encode into the instruction. For example, the ARM shifted immediate and
shifted register operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116353 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 22:21:57 +00:00
Bill Wendling
174777bb2b Encoding for VADDD. Plus a test for the VFP instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116348 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 22:08:41 +00:00
Bill Wendling
a0c14ef8f6 Split out the "size" field from the encoding. The newer documentation has it as 
a separate bit in the coding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116347 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 22:03:19 +00:00
Eric Christopher
558cf007b5 Fix thinko in arm fast isel alloca rewrite. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116339 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 21:23:43 +00:00
Jim Grosbach
499e886fe6 Encoding for ARM-mode VADD.F32 instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116338 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 21:22:40 +00:00
Owen Anderson
2ab36d3502 Begin adding static dependence information to passes, which will allow us to 
perform initialization without static constructors AND without explicit initialization
by the client.  For the moment, passes are required to initialize both their
(potential) dependencies and any passes they preserve.  I hope to be able to relax
the latter requirement in the future.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116334 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 19:48:12 +00:00
Eric Christopher
52b45056b2 Combine these together - should probably have some text associated 
that says what why what we just asserted is wrong.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116333 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 19:44:17 +00:00
Michael J. Spencer
09203ac3dd KillTheDoctor: Fix VS2008 build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116330 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 19:27:44 +00:00
Nick Lewycky
65b65d6ca4 Mark variable 'NoImplicitFloatOps' used only in an assert as used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116323 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 18:18:03 +00:00
Jim Grosbach
82635f080c Comment grammar tweakage. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116322 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 18:11:41 +00:00
Jim Grosbach
f59818b81a Add MOVi ARM encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116321 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 18:09:12 +00:00
Dan Gohman
320afb8c81 Initial va_arg support for x86-64. Patch by David Meyer! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116319 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 18:00:49 +00:00
Jim Grosbach
8e157302f4 Nuke unused wrapper function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116318 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 17:53:25 +00:00
Jakob Stoklund Olesen
d0eeeeb558 Remove the x86 MOV{32,64}{rr,rm,mr}_TC instructions. 
The reg-reg copies were no longer being generated since copyPhysReg copies
physical registers only.

The loads and stores are not necessary - The TC constraint is imposed by the
TAILJMP and TCRETURN instructions, there should be no need for constrained loads
and stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116314 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 17:15:00 +00:00
Jim Grosbach
0de6ab3c43 Add encoding information for the remainder of the generic arithmetic 
ARM instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116313 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 17:11:26 +00:00
Bob Wilson
77f42b5278 PR8359: The ARM backend may end up allocating registers D16 to D31 when 
"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers.  Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116310 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 16:22:47 +00:00
Eric Christopher
1541877941 Rework alloca handling so that we can load or store from casted 
address that we've looked through.

Fixes compilation problems in tramp3d from earlier patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116296 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 05:39:06 +00:00
Eric Christopher
14074e8ec4 Fix the last two commits to configure - configure is a generated file. 
Made necessary edits to configure.ac and regenerated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116291 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 02:42:05 +00:00
Eric Christopher
5532433a57 Handle a wider arrangement of loads. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116284 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 00:43:21 +00:00
Cameron Esfahani
519c893c26 Fix spelling error. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116282 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 00:21:05 +00:00
Dan Gohman
624218f5b4 Delete a redundant check. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116280 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 00:19:24 +00:00
Dan Gohman
9b0e47efc6 More SmallVectorImpls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116279 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 00:15:27 +00:00
Dan Gohman
8de206c101 Shrink a SmallVector with a known maximum size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116278 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 00:13:43 +00:00
Dan Gohman
568a63db96 Constify. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116277 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 00:12:29 +00:00
Dan Gohman
ebb1834e86 Use SmallVectorImpl in a bunch of places. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116276 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 00:11:18 +00:00
Francois Pichet
b2b9b768ef Disable warning C4267 for MSVC. Otherwise it generate literally thousands of warnings when targeting x64. The warning occurs because int is 32 bit but size_t is 64 bit on Win64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116274 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 00:01:36 +00:00
Dan Gohman
c015723131 Add a simple testcase for tbaa. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116272 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 23:54:13 +00:00
Evan Cheng
08cec1ef27 More ARM scheduling itinerary fixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116266 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 23:41:41 +00:00
Dan Gohman
633e702317 Support AA chaining. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116264 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 23:39:34 +00:00
Dan Gohman
7c34730fb9 Fix the pass manager's search order for immutable passes, and make it 
stop searching when it has found a match.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116262 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 23:19:01 +00:00