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Author SHA1 Message Date
Chris Lattner
13c78e2e5f legalize ANY_EXTEND appropriately 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23204 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-02 00:18:10 +00:00
Chris Lattner
4ed11b4b79 Add support for ANY_EXTEND and add a few minor folds for it 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23203 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-02 00:17:32 +00:00
Chris Lattner
fb8b8a75ff Handle any_extend like zext 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23202 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-02 00:16:09 +00:00
Chris Lattner
26e04bbf77 Handle ANY_EXTEND like ZERO_EXTEND. Simplify the extend/truncate code on 
the observation that it only has to handle i1 -> i64 and i64 -> i1.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23201 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-02 00:15:30 +00:00
Chris Lattner
7e122db776 Add a new ANY_EXTEND node, which operates like an extension but has undefined 
top bits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23200 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-02 00:14:40 +00:00
Chris Lattner
7dd8b05fd7 This should permit NOT and's, not even dead ones. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23199 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-02 00:13:56 +00:00
Chris Lattner
2a00daac58 Implement small-arguments.ll:test3 by teaching the DAG optimizer that 
the results of calls to functions returning small values are properly
sign/zero extended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23198 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-01 23:44:32 +00:00
Chris Lattner
9832ce0f0a Another case that shouldn't have sign extends: functions returning short 
are known to return properly sign extended values, no need for an explicit
extension.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23197 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-01 23:43:58 +00:00
Nate Begeman
39f60a2302 Fix some code in the current node combining code, spotted when it was moved 
over to DAGCombiner.cpp

1. Don't assume that SetCC returns i1 when folding (xor (setcc) constant)
2. Don't duplicate code in folding AND with AssertZext that is handled by
   MaskedValueIsZero


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23196 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-01 23:25:49 +00:00
Nate Begeman
4ebd805c6a Implement first round of feedback from chris (there's still a couple things 
left to do).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23195 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-01 23:24:04 +00:00
Chris Lattner
2b8ad8e55a Align functions to 16-byte boundaries, to eliminate noise in performance measurements. This improves the performance of 'treeadd' by about 20% with the dag 
isel, restoring it to the pattern-isel level (which happens to get the alignment right).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23194 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-01 23:08:50 +00:00
Chris Lattner
a82f7b2be0 Local labels on darwin apparently start with just 'L', not .L like other 
platforms.  This reduces executable size and makes shark realize the actual
bounds of functions instead of showing each MBB as a function :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23193 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-01 21:48:35 +00:00
Jim Laskey
b1e1180ca0 1. Use SubtargetFeatures in llc/lli. 
2. Propagate feature "string" to all targets.

3. Implement use of SubtargetFeatures in PowerPCTargetSubtarget.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23192 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-01 21:38:21 +00:00
Jim Laskey
b3302db18a This new class provides support for platform specific "features". The intent 
is to manage processor specific attributes from the command line.  See examples
of use in llc/lli and PowerPCTargetSubtarget.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23191 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-01 21:36:18 +00:00
Chris Lattner
75592e4137 Implement dynamic allocas correctly. In particular, because we were copying 
directly out of R1 (without using a CopyFromReg, which uses a chain), multiple
allocas were getting CSE'd together, producing bogus code.  For this:

int %foo(bool %X, int %A, int %B) {
        br bool %X, label %T, label %F
F:
        %G = alloca int
        %H = alloca int
        store int %A, int* %G
        store int %B, int* %H
        %R = load int* %G
        ret int %R
T:
        ret int 0
}

We were generating:

_foo:
        stwu r1, -16(r1)
        stw r31, 4(r1)
        or r31, r1, r1
        stw r1, 12(r31)
        cmpwi cr0, r3, 0
        bne cr0, .LBB_foo_2     ; T
.LBB_foo_1:     ; F
        li r2, 16
        subf r2, r2, r1   ;; One alloca
        or r1, r2, r2
        or r3, r1, r1
        or r1, r2, r2
        or r2, r1, r1
        stw r4, 0(r3)
        stw r5, 0(r2)
        lwz r3, 0(r3)
        lwz r1, 12(r31)
        lwz r31, 4(r31)
        lwz r1, 0(r1)
        blr
.LBB_foo_2:     ; T
        li r3, 0
        lwz r1, 12(r31)
        lwz r31, 4(r31)
        lwz r1, 0(r1)
        blr

Now we generate:

_foo:
        stwu r1, -16(r1)
        stw r31, 4(r1)
        or r31, r1, r1
        stw r1, 12(r31)
        cmpwi cr0, r3, 0
        bne cr0, .LBB_foo_2     ; T
.LBB_foo_1:     ; F
        or r2, r1, r1
        li r3, 16
        subf r2, r3, r2  ;; Alloca 1
        or r1, r2, r2
        or r2, r1, r1
        or r6, r1, r1
        subf r3, r3, r6  ;; Alloca 2
        or r1, r3, r3
        or r3, r1, r1
        stw r4, 0(r2)
        stw r5, 0(r3)
        lwz r3, 0(r2)
        lwz r1, 12(r31)
        lwz r31, 4(r31)
        lwz r1, 0(r1)
        blr
.LBB_foo_2:     ; T
        li r3, 0
        lwz r1, 12(r31)
        lwz r31, 4(r31)
        lwz r1, 0(r1)
        blr

This fixes Povray and SPASS with the dag isel, the last two failing cases.
Tommorow we will hopefully turn it on by default! :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23190 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-01 21:31:30 +00:00
Chris Lattner
393ecd6d2d Fix a bug where we were useing HA to get the high part, which seems like it 
could cause a miscompile.  Fixing this didn't fix the two programs that fail
though.  :(

This also changes the implementation to follow the pattern selector more
closely, causing us to select 0 to li instead of lis.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23189 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-01 19:38:28 +00:00
Chris Lattner
50ff55c2c7 Do not select the operands being passed into SelectCC. IT does this itself 
and selecting early prevents folding immediates into the cmpw* instructions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23188 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-01 19:20:44 +00:00
Chris Lattner
da8abb0239 It is NDEBUG not _NDEBUG 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23186 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-01 18:44:10 +00:00
Nate Begeman
4942a9687d Add the rest of the currently implemented visit routines to the switch 
statement in visit().


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23185 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-01 00:33:32 +00:00
Nate Begeman
1d4d414111 First pass at the DAG Combiner. It isn't used anywhere yet, but it should 
be mostly functional.  It currently has all folds from SelectionDAG.cpp
that do not involve a condition code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23184 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-01 00:19:25 +00:00
Nate Begeman
feca19b0d4 Add regression test for efficient codegen of i32 x i32 -> hi32(i64) as 
mulhs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23183 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-01 00:04:03 +00:00
Chris Lattner
67d2562be7 remove an inappropriate comment 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23182 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-31 22:49:51 +00:00
Chris Lattner
a1f68ca94e If a function has live ins/outs, print them 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23181 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-31 22:34:59 +00:00
Chris Lattner
f76053269e Move FCTIWZ handling out of the instruction selectors and into legalization, 
getting them out of the business of making stack slots.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23180 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-31 21:09:52 +00:00
Chris Lattner
8346bb6c29 Remove dead code 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23179 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-31 20:25:15 +00:00
Chris Lattner
bc11c3482c Move SHL,SHR i64 -> legalizer 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23178 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-31 20:23:54 +00:00
Chris Lattner
c22af9e5df Remove code that is now dead from the pattern isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23177 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-31 19:11:36 +00:00
Chris Lattner
eb9b62e35e lower sra_parts on the dag, implementing it for the dag isel, and exposing 
the ops to dag optimization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23176 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-31 19:09:57 +00:00
Chris Lattner
50ec897904 Allow targets to custom expand shifts that are too large for their registers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23173 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-31 19:01:53 +00:00
Chris Lattner
c730706a89 Add a testcase for nate's patch 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23172 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-31 18:19:50 +00:00
Chris Lattner
99296ffd36 add assert zext/sext to the dag isel 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23171 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-31 18:08:46 +00:00
Chris Lattner
5dd7fea3f2 Handle AssertSext/AssertZext nodes, fixing the regressions last night. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23170 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-31 17:48:04 +00:00
Jeff Cohen
7383ce4127 Fix VC++ precedence warnings 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23169 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-31 02:47:06 +00:00
Nate Begeman
49296f1f48 Enable generation of AssertSext and AssertZext in the PPC backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23168 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-31 01:58:39 +00:00
Chris Lattner
7a49fdcd11 Fix 'ret long' to return the high and lo parts in the right registers. This 
fixes crafty and probably others.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23167 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-31 01:34:29 +00:00
Nate Begeman
fe75a2836a Sigh, not my day. Fix typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23166 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-31 00:43:49 +00:00
Nate Begeman
9f52f2838d Fix a mistake in my previous patch pointed out by sabre; the AssertZext 
case in MaskedValueIsZero was wrong.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23165 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-31 00:43:08 +00:00
Nate Begeman
b85dfab889 Remove some unnecessary casts, and add the AssertZext case to 
MaskedValueIsZero.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23164 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-31 00:27:53 +00:00
Nate Begeman
16d6ea5264 Add support for count trailing zeroes, and population count. These are 
needed for folding constants in the upcoming dag combiner.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23163 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-31 00:25:01 +00:00
Chris Lattner
eb80fe8ff6 now that physregs can exist in the same dag with multiple types, remove some 
ugly hacks


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23162 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-30 22:59:48 +00:00
Chris Lattner
0fdd768094 Allow physregs to occur in the dag with multiple types. Though I don't likethis, it is a requirement on PPC, which can have an f32 value in r3 at onepoint in a function and a f64 value in r3 at another point. :( 
This fixes compilation of mesa


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23161 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-30 22:38:38 +00:00
Chris Lattner
d6a80778e5 Allow physregs to occur in the dag with multiple types. Though I don't like 
this, it is a requirement on PPC, which can have an f32 value in r3 at one
point in a function and a f64 value in r3 at another point.  :(


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23160 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-30 22:38:05 +00:00
Chris Lattner
2ea0c66ae5 Fix type mismatches when passing f32 values to calls 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23159 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-30 21:28:19 +00:00
Chris Lattner
e836ad6736 When checking the fixed intervals, don't forget to check for register aliases. 
This fixes PR621 and Regression/CodeGen/X86/2005-08-30-RegAllocAliasProblem.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23158 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-30 21:03:36 +00:00
Chris Lattner
353f1dea50 new testcase corresponding to PR621 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23157 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-30 21:02:51 +00:00
Chris Lattner
dd43c866c8 The dag isel misses both of these, the pattern isel just misses the second 
one.  TODO :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23156 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-30 18:44:09 +00:00
Chris Lattner
1368721d53 Fix some indentation (first hunks). 
Remove code (last hunk) that miscompiled immediate and's, such as
  and uint %tmp.30, 4294958079

into

 andi. r8, r8, 56319
 andis. r8, r8, 65535

instead of:

 li r9, -9217
 and r8, r8, r9

The first always generates zero.

This fixes espresso.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23155 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-30 18:37:48 +00:00
Chris Lattner
b551ba7661 Fix a problem Nate found where we swapped the operands of SHL/SHR_PARTS. This 
fixes fourinarow


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23153 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-30 17:42:59 +00:00
Chris Lattner
14b86c72a2 codegen ADD_PARTS correctly: put the results in the right registers! This 
fixes fhourstones


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23152 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-30 17:40:13 +00:00
Chris Lattner
cc0675a4be Fix FreeBench/fourinarow with the dag isel, by not adding a bogus result 
to SHIFT_PARTS nodes


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23151 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-30 17:21:17 +00:00