Commit Graph

139 Commits

Author SHA1 Message Date
David Greene
9b9838dbd4 Add more vector ValueTypes for AVX and other extended vector instruction
sets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74427 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-29 16:47:10 +00:00
Dale Johannesen
874ae251c3 Revert 72707 and 72709, for the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72712 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-02 03:12:52 +00:00
Dale Johannesen
4150d83abe Make the implicit inputs and outputs of target-independent
ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to)
instead of MVT::Flag.  Remove CARRY_FALSE in favor of 0; adjust
all target-independent code to use this format.

Most targets will still produce a Flag-setting target-dependent
version when selection is done.  X86 is converted to use i32
instead, which means TableGen needs to produce different code
in xxxGenDAGISel.inc.  This keys off the new supportsHasI1 bit
in xxxInstrInfo, currently set only for X86; in principle this
is temporary and should go away when all other targets have
been converted.  All relevant X86 instruction patterns are
modified to represent setting and using EFLAGS explicitly.  The
same can be done on other targets.

The immediate behavior change is that an ADC/ADD pair are no
longer tightly coupled in the X86 scheduler; they can be
separated by instructions that don't clobber the flags (MOV).
I will soon add some peephole optimizations based on using
other instructions that set the flags to feed into ADC.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72707 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-01 23:27:20 +00:00
Bob Wilson
d305e707a6 Fix PR3994: LLVMMatchType arguments do not refer to absolute return value
and argument positions but only to the overloaded intrinsic parameters.
Keep a separate list of these overloaded parameters in CodeGenTarget.cpp
so they can be resolved easily.  Remove assertions from IntrinsicEmitter.cpp:
they were harmless but confusing, and the assertions elsewhere in TableGen
will catch any incorrect values.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69316 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-16 21:51:05 +00:00
Dan Gohman
88c7af096b Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalize
it accordingly. Thanks to Jakob Stoklund Olesen for pointing
out how this might be useful.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 21:06:25 +00:00
Dan Gohman
f8c7394781 Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.
This will be used to replace things like X86's MOV32to32_.

Enhance ScheduleDAGSDNodesEmit to be more flexible and robust
in the presense of subregister superclasses and subclasses. It
can now cope with the definition of a virtual register being in
a subclass of a use.

Re-introduce the code for recording register superreg classes and
subreg classes. This is needed because when subreg extracts and
inserts get coalesced away, the virtual registers are left in
the correct subclass.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68961 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 15:38:05 +00:00
Dale Johannesen
49de98214b Reapply 63765. Patches for clang and llvm-gcc to follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63812 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-05 01:49:45 +00:00
Dale Johannesen
4d452de150 Reverting 63765. This broke the build of both clang
and llvm-gcc.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63786 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-04 22:47:25 +00:00
Nate Begeman
d24479730a New feature: add support for target intrinsics being defined in the
target directories themselves.  This also means that VMCore no longer
needs to know about every target's list of intrinsics.  Future work
will include converting the PowerPC target to this interface as an
example implementation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63765 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-04 19:47:21 +00:00
Chris Lattner
a62c302ddd add nocapture attribute to llvm.mem* intrinsics and have tblgen
parse them.  tblgen doesn't yet do anything with this info though.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62065 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-12 01:12:03 +00:00
Bob Wilson
bc03979536 Improve support for type-generic vector intrinsics by teaching TableGen how
to handle LLVMMatchType intrinsic parameters, and by adding new subclasses
of LLVMMatchType to match vector types with integral elements that are 
either twice as wide or half as wide as the elements of the matched type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61834 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-07 00:09:01 +00:00
Mon P Wang
87c8a8f304 Added support for vector widening.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61209 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-18 20:03:17 +00:00
Bill Wendling
cdcc3e6e12 Modify the intrinsics pattern to separate out the "return" types from the
"parameter" types. An intrinsic can now return a multiple return values like
this:

  def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty],
                                    [LLVMMatchType<0>, LLVMMatchType<0>]>;



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Dan Gohman
1e0ee4bc38 Factor the code for determining the target-specific instruction
namespace out of the isel emitters and into common code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55079 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-20 21:45:57 +00:00
Dan Gohman
ba6783ec8c Fix the string for MVT::isVoid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55034 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-20 01:44:30 +00:00
Mon P Wang
e3b3a7241c Added support for overloading intrinsics (atomics) based on pointers
to different address spaces.  This alters the naming scheme for those
intrinsics, e.g., atomic.load.add.i32 => atomic.load.add.i32.p0i32


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54195 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-30 04:36:53 +00:00
Dan Gohman
4406604047 Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating
the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.

Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.

This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52943 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-01 00:05:16 +00:00
Mon P Wang
2887310630 Added MemOperands to Atomic operations since Atomics touches memory.
Added abstract class MemSDNode for any Node that have an associated MemOperand
Changed atomic.lcs => atomic.cmp.swap, atomic.las => atomic.load.add, and
atomic.lss => atomic.load.sub


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52706 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-25 08:15:39 +00:00
Evan Cheng
6bd9567a6a - Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code.
- Mark lots of X86 intrinsics as "Commutative" to allow load folding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
Duncan Sands
83ec4b6711 Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction.  Rename the type
to MVT.  To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits().  Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-06 12:08:01 +00:00
Dan Gohman
ee4fa1977d Move instruction flag inference out of InstrInfoEmitter and into
CodeGenDAGPatterns, where it can be used in other tablegen backends.
This allows the inference to be done for DAGISelEmitter so that it
gets accurate mayLoad/mayStore/isSimpleLoad flags. 

This brings MemOperand functionality back to where it was before
48329. However, it doesn't solve the problem of anonymous patterns
which expand to code that does loads or stores.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49123 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-03 00:02:49 +00:00
Christopher Lamb
c929823525 Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48412 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-16 03:12:01 +00:00
Evan Cheng
da47e6e0d0 Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48380 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-15 00:03:38 +00:00
Evan Cheng
a844bdeab3 SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc.
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46659 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-02 04:07:54 +00:00
Christopher Lamb
8535624739 Allow ComplexExpressions in InstrInfo.td files to be slightly more... complex! ComplexExpressions can now have attributes which affect how TableGen interprets
the pattern when generating matchin code. 

The first (and currently, only) attribute causes the immediate parent node of the ComplexPattern operand to be passed into the matching code rather than the node at the root of the entire DAG containing the pattern.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46606 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-31 07:27:46 +00:00
Chris Lattner
ba7e756c22 Start inferring side effect information more aggressively, and fix many bugs in the
x86 backend where instructions were not marked maystore/mayload, and perf issues where
instructions were not marked neverHasSideEffects.  It would be really nice if we could
write patterns for copy instructions.

I have audited all the x86 instructions down to MOVDQAmr.  The flags on others and on
other targets are probably not right in all cases, but no clients currently use this
info that are enabled by default.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45829 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-10 07:59:24 +00:00
Chris Lattner
6cc654b27a Split the impl of CodeGenInstruction out to its own .cpp file, add a getName() accessor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45645 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-06 01:35:39 +00:00
Chris Lattner
6cefb77a70 change getQualifiedName to be a global function.
Split the pattern parsing code out from the dag isel emitter into it's own file.

No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45632 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-05 22:25:12 +00:00
Chris Lattner
3060910e29 remove attributions from utils.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45419 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-29 20:37:13 +00:00
Bill Wendling
6b1da9c39f Add flags to indicate that there are "never" side effects or that there "may be"
side effects for machine instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45022 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-14 01:48:59 +00:00
Evan Cheng
3dd298fb62 Oops. Forgot these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44969 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-13 00:42:35 +00:00
Owen Anderson
20ab29068d Add a flag for indirect branch instructions.
Target maintainers: please check that the instructions for your target are correctly marked.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44012 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-12 07:39:39 +00:00
Dale Johannesen
317096ab37 Add sqrt and powi intrinsics for long double.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42423 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-28 01:08:20 +00:00
Evan Cheng
a3ca3149f2 Add CopyCost to TargetRegisterClass. This specifies the cost of copying a value
between two registers in the specific class.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42123 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-19 01:35:01 +00:00
Dan Gohman
0fee3ff93e Add MVT::fAny for overloading intrinsics on floating-point types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41128 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-16 21:57:19 +00:00
Chandler Carruth
6994040a95 This is the patch to provide clean intrinsic function overloading support in LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future.
This also changes the syntax for llvm.bswap, llvm.part.set, llvm.part.select, and llvm.ct* intrinsics. They are automatically upgraded by both the LLVM ASM reader and the bitcode reader. The test cases have been updated, with special tests added to ensure the automatic upgrading is supported.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40807 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-04 01:51:18 +00:00
Christopher Lamb
08d52071ba Add target independent MachineInstr's to represent subreg insert/extract in MBB's. PR1350
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40518 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-26 07:48:21 +00:00
Christopher Lamb
8245510ae0 Teach TableGen about the new vector types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40513 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-26 06:41:18 +00:00
Evan Cheng
102dc195b6 No need for noResults anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40075 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-20 00:21:23 +00:00
Evan Cheng
64d80e3387 Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
Dan Gohman
3bf6e183d5 Eliminate an unused parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39828 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-13 20:16:50 +00:00
Evan Cheng
88cc092ca5 Try committing again. Add OptionalDefOperand. Remove clobbersPred.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38498 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-10 18:05:01 +00:00
Evan Cheng
c419bd3396 ImmutablePredicateOperand is no more.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37963 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-06 23:23:38 +00:00
Evan Cheng
8012b077dd Instructions with ImmutablePredicateOperand aren't really predicable since their predicates are fixed at isel time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37899 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-05 07:19:29 +00:00
Dan Gohman
d45eddd214 Revert the earlier change that removed the M_REMATERIALIZABLE machine
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37728 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-26 00:48:07 +00:00
Dan Gohman
82a87a0172 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37644 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-19 01:48:05 +00:00
Evan Cheng
eaa91b0a1f Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37643 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-19 01:26:51 +00:00
Christopher Lamb
a321125e8b Add support to tablegen for specifying subregister classes on a per register class basis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37572 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-13 22:20:15 +00:00
Evan Cheng
b5c1c9c8e3 Add clobbersPred - instruction that clobbers condition code / register which are used to predicate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37465 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-06 10:14:55 +00:00
Dan Gohman
b9daee9ece Remove the operator<< for MVT::ValueType in preparation for MVT::ValueType
being changed from an enum to an integer type, which can't have a custom
operator<< overload.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37412 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-04 16:11:03 +00:00