Commit Graph

1672 Commits

Author SHA1 Message Date
Evan Cheng
2457f2c661 Implement @llvm.returnaddress. rdar://8015977.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104421 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 01:47:14 +00:00
Eric Christopher
46099f14dc Add a new section and accessor for TLS data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104411 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 00:00:58 +00:00
Matt Fleming
d8a33ddcfe Currently, createMachOStreamer() is invoked directly in llvm-mc which
isn't ideal if we want to be able to use another object file format.

Add a createObjectStreamer() factory method so that the correct object
file streamer can be instantiated for a given target triple.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104318 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 12:54:43 +00:00
Evan Cheng
1cc3984148 Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104293 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 23:26:43 +00:00
Daniel Dunbar
4072886a69 tblgen/Target: Add a isAsmParserOnly bit, and teach the disassembler to honor
it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104270 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:20:32 +00:00
Evan Cheng
15a16def6e Add a hybrid bottom up scheduler that reduce register usage while avoiding
pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot
of long latency instructions so a strict register pressure reduction
scheduler does not work well.
Early experiments show this speeds up some NEON loops by over 30%.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104216 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 06:13:19 +00:00
Evan Cheng
211ffa1351 Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104147 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 20:19:50 +00:00
Evan Cheng
06b666c705 Allow TargetLowering::getRegClassFor() to be called on illegal types. Also
allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 02:18:07 +00:00
Evan Cheng
b990a2f249 Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE
instructions.

e.g.
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1027<def> = EXTRACT_SUBREG %reg1026, 6
%reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5
...
%reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12

After REG_SEQUENCE is eliminated, we are left with:

%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
%reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5

The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't
know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the
target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger
sub-register (or combined to be reg1026 itself as is the case here). If it is possible, 
it will be able to replace references of reg1026 with reg1029 + the larger sub-register
index.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103835 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 23:21:14 +00:00
Evan Cheng
0ebf356ddf Get rid of the bit twiddling to read / set OpActions and ValueTypeActions. The small saving in memory isn't worth the increase in runtime and code complexity in my opinion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103768 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 07:37:40 +00:00
Evan Cheng
b9c0e332b3 Eliminate use of magic numbers to access OpActions. It also has the effect of allowing more than 31 scalar value types. MAX_ALLOWED_VALUETYPE had already been updated to 64 a while back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103743 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 23:25:21 +00:00
Evan Cheng
b21f5a5511 Fix up LoadExtActions, TruncStoreActions, and IndexedModeActions representation and setter and getter's so they will continue to work if the number of scalar ValueType's exceeds 31.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103742 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 23:01:26 +00:00
Evan Cheng
1e5a6c46b8 80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103733 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 20:14:58 +00:00
Daniel Dunbar
a5f1d57f65 MC/Mach-O/x86_64: Add a new hook for checking whether a particular section can
be diced into atoms, and adjust getAtom() to take this into account.
 - This fixes relocations to symbols in fixed size literal sections, for
   example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103532 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-12 00:38:17 +00:00
Dan Gohman
99dca4fde7 Remove the "WantsWholeFile" concept, as it's no longer needed. CBE
and the others use the regular addPassesToEmitFile hook now, and
llc no longer needs a bunch of redundant code to handle the
whole-file case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103492 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 19:57:55 +00:00
Dan Gohman
038df88e28 Trim #includes and forward declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103489 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 19:11:43 +00:00
Dan Gohman
17c4a621fe Fix a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103483 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 18:03:41 +00:00
Dan Gohman
ff7a562751 Implement a bunch more TargetSelectionDAGInfo infrastructure.
Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103481 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 17:31:57 +00:00
Dan Gohman
419e4f9263 Remove the TargetLowering::getSubtarget() virtual function, which
was unused. TargetMachine::getSubtarget() is used instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103474 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 16:21:03 +00:00
Bill Wendling
81043ee5dc The getDefaultSubtargetFeatures method of SubtargetFeature did actually return a
string of features for that target. However LTO was using that string to pass
into the "create target machine" stuff. That stuff needed the feature string to
be in a particular form. In particular, it needed the CPU specified first and
then the attributes. If there isn't a CPU specified, it required it to be blank
-- e.g., ",+altivec". Yuck.

Modify the getDefaultSubtargetFeatures method to be a non-static member
function. For all attributes for a specific subtarget, it will add them in like
normal. It will also take a CPU string so that it can satisfy this horrible
syntax.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103451 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 00:30:02 +00:00
Dan Gohman
34dcc6fadc Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
doesn't have to guess.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 20:33:48 +00:00
Evan Cheng
746ad69e08 Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103193 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 19:06:44 +00:00
Daniel Dunbar
4f83e73a6d MC/Matcher: Add support for over-riding the default MatchInstruction function
name (for example, to allow targets to interpose the actual MatchInstruction
function).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102987 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04 00:33:13 +00:00
Duncan Sands
57b6e9eb6c Remove the -enable-sjlj-eh option, which doesn't do anything.
Remove the -enable-eh option which is only used by the JIT,
and replace it with -jit-enable-eh.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102865 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-02 15:36:26 +00:00
Evan Cheng
b55c8bed9d Add a pseudo instruction REG_SEQUENCE that takes a list of registers and
sub-register indices and outputs a single super register which is formed from
a consecutive sequence of registers.

This is used as register allocation / coalescing aid and it is useful to
represent instructions that output register pairs / quads. For example,
v1024, v1025 = vload <address>
where v1024 and v1025 forms a register pair.

This really should be modelled as
v1024<3>, v1025<4> = vload <address>
but it would violate SSA property before register allocation is done.

Currently we use insert_subreg to form the super register:
v1026 = implicit_def
v1027 - insert_subreg v1026, v1024, 3
v1028 = insert_subreg v1027, v1025, 4
...
      = use v1024
      = use v1028

But this adds pseudo live interval overlap between v1024 and v1025.

We can now modeled it as
v1024, v1025 = vload <address>
v1026 = REG_SEQUENCE v1024, 3, v1025, 4
...
      = use v1024
      = use v1026

After coalescing, it will be
v1026<3>, v1025<4> = vload <address>
...
      = use v1026<3>
      = use v1026


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102815 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-01 00:28:44 +00:00
Dan Gohman
af1d8ca44a Get rid of the EdgeMapping map. Instead, just check for BasicBlock
changes before doing phi lowering for switches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-01 00:01:06 +00:00
Evan Cheng
8601a3d4de Frame index can be negative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102577 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-29 01:13:30 +00:00
Chris Lattner
ee9eb411ff on darwin empty functions need to codegen into something of non-zero length,
otherwise labels get incorrectly merged.  We handled this by emitting a 
".byte 0", but this isn't correct on thumb/arm targets where the text segment
needs to be a multiple of 2/4 bytes.  Handle this by emitting a noop.  This
is more gross than it should be because arm/ppc are not fully mc'ized yet.

This fixes rdar://7908505



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102400 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-26 23:37:21 +00:00
Dale Johannesen
efc3a6348a Add PPC AsmPrinter handling for target-specific form of
DBG_VALUE, and a cautionary comment.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102371 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-26 20:05:01 +00:00
Evan Cheng
962021bc7f - Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue.
- Teach spiller to modify DBG_VALUE instructions to reference spill slots.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102323 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-26 07:38:55 +00:00
Dale Johannesen
f822e733af Stop abusing EmitInstrWithCustomInserter for target-dependent
form of DEBUG_VALUE, as it doesn't have reasonable default
behavior for unsupported targets.  Add a new hook instead.
No functional change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102320 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-25 21:33:54 +00:00
Dan Gohman
f81eca0ab9 Move HandlePHINodesInSuccessorBlocks functions out of SelectionDAGISel
and into SelectionDAGBuilder and FastISel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102123 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-22 20:46:50 +00:00
Evan Cheng
e566763b19 Implement -disable-non-leaf-fp-elim which disable frame pointer elimination
optimization for non-leaf functions. This will be hooked up to gcc's
-momit-leaf-frame-pointer option. rdar://7886181


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101984 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21 03:18:23 +00:00
Dan Gohman
f0757b0edc Add more const qualifiers on TargetMachine and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101977 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21 01:34:56 +00:00
Dale Johannesen
7609017dc3 Because of the EMMS problem, right now we have to support
user-defined operations that use MMX register types, but
the compiler shouldn't generate them on its own.  This adds
a Synthesizable abstraction to represent this, and changes
the vector widening computation so it won't produce MMX types.
(The motivation is to remove noise from the ABI compatibility
part of the gcc test suite, which has some breakage right now.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101951 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 22:34:09 +00:00
Dan Gohman
e08b320f15 Document that TargetRegisterInfo::contains does not cover virtual registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 14:51:20 +00:00
Anton Korobeynikov
928eb49cae Make processor FUs unique for given itinerary. This extends the limit of 32
FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101754 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-18 20:31:01 +00:00
Dan Gohman
d858e90f03 Use const qualifiers with TargetLowering. This eliminates several
const_casts, and it reinforces the design of the Target classes being
immutable.

SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.

And PIC16's AsmPrinter no longer uses TargetLowering.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101635 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 15:26:15 +00:00
Evan Cheng
e5b51ac770 More work to allow dag combiner to promote 16-bit ops to 32-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101621 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 06:13:15 +00:00
Dan Gohman
abf0c3475a Add a getSelectionDAGInfo member to TargetMachine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101567 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 23:09:10 +00:00
Dan Gohman
8c0e89925d Create a new TargetSelectionDAGInfo class. This will eventually acquire
SelectionDAG-specific parts of TargetLowering.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101537 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 21:12:11 +00:00
Dan Gohman
37f32ee7ff Eliminate an unnecessary SelectionDAG dependency in getOptimalMemOpType.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101531 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 20:11:05 +00:00
Dan Gohman
7f506a9c7f Fix this code to avoid implicit assumptions about the length of the array.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101530 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 20:08:45 +00:00
Evan Cheng
64b7bf71e8 Adding support for dag combiner to promote operations for profit. This requires target specific queries. For example, x86 should promote i16 to i32 when it does not impact load folding.
x86 support is off by default. It can be enabled with -promote-16bit.

Work in progress.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101448 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 06:14:10 +00:00
Dan Gohman
46510a73e9 Add const qualifiers to CodeGen's use of LLVM IR constructs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101334 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 01:51:59 +00:00
Dan Gohman
2520864773 Factor out EH landing pad code into a separate function, and constify
a bunch of stuff to support it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101273 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-14 19:53:31 +00:00
Chris Lattner
43ac721e3b add llvm codegen support for -ffunction-sections and -fdata-sections,
patch by Sylvere Teissier!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101106 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-13 00:36:43 +00:00
Evan Cheng
c3b0c341e7 Avoid using f64 to lower memcpy from constant string. It's cheaper to use i32 store of immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100751 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-08 07:37:57 +00:00
Evan Cheng
2dbc8bdfe9 Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100726 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 23:51:38 +00:00
Anton Korobeynikov
4b38debf59 Remove late ARM codegen optimization pass committed by accident.
It is not ready for public yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100673 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:23:27 +00:00