Commit Graph

20420 Commits

Author SHA1 Message Date
Daniel Dunbar
24ec2e5a72 [tests] Cleanup initialization of test suffixes.
- Instead of setting the suffixes in a bunch of places, just set one master
   list in the top-level config. We now only modify the suffix list in a few
   suites that have one particular unique suffix (.ml, .mc, .yaml, .td, .py).

 - Aside from removing the need for a bunch of lit.local.cfg files, this enables
   4 tests that were inadvertently being skipped (one in
   Transforms/BranchFolding, a .s file each in DebugInfo/AArch64 and
   CodeGen/PowerPC, and one in CodeGen/SI which is now failing and has been
   XFAILED).

 - This commit also fixes a bunch of config files to use config.root instead of
   older copy-pasted code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188513 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-16 00:37:11 +00:00
Jim Grosbach
4658ce9c1f InstCombine: Simplify if(x!=0 && x!=-1).
When both constants are positive or both constants are negative,
InstCombine already simplifies comparisons like this, but when
it's exactly zero and -1, the operand sorting ends up reversed
and the pattern fails to match. Handle that special case.

Follow up for rdar://14689217

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188512 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-16 00:15:20 +00:00
Matt Arsenault
a630cb032c Don't do FoldCmpLoadFromIndexedGlobal for non inbounds GEPs
This path wasn't tested before without a datalayout,
so add some more tests and re-run with and without one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188507 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-15 23:11:07 +00:00
Daniel Dunbar
212cb346a8 [tests] Fix refacto in r187764 that effectively disabled SimplifyCFG tests. :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188503 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-15 22:52:27 +00:00
Yunzhong Gao
b187b69170 Fixing a corner-case bug in strchr and strrchr lib call optimizations where
the input character is not converted to char before comparing with zero.

The patch was discussed in this thread:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130812/184069.html



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188489 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-15 20:58:59 +00:00
Peter Collingbourne
a77d9f726a DataFlowSanitizer: Add a debugging feature to help us track nonzero labels.
Summary:
When the -dfsan-debug-nonzero-labels parameter is supplied, the code
is instrumented such that when a call parameter, return value or load
produces a nonzero label, the function __dfsan_nonzero_label is called.
The idea is that a debugger breakpoint can be set on this function
in a nominally label-free program to help identify any bugs in the
instrumentation pass causing labels to be introduced.

Reviewers: eugenis

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1405

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188472 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-15 18:51:12 +00:00
Mihai Popa
428715d4e1 This fixes three issues related to Thumb literal loads:
1. The offset range for Thumb1 PC relative loads is [0..1020] and not [-1024..1020]
2. Thumb2 PC relative loads may define the PC, so the restriction placed on target register is removed
3. Removes unneeded alias between "ldr.n" and t1LDRpci. ".n" is actually stripped by both tablegen
and the ASM parser, so this alias rule really does nothing


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188466 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-15 15:43:06 +00:00
Jack Carter
bd71eea899 [Mips][msa] Added the simple builtins (madd_q to xori)
Includes:
madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su],
msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev,
pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al],
sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori

Patch by Daniel Sanders


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188460 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-15 14:22:07 +00:00
Jack Carter
d0f99639c1 [Mips][msa] Added the simple builtins (fadd to ftq)
Includes:
fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2,
fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin,
fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt,
fsne, fsqr, fsub, ftint_s, ftq

Patch by Daniel Sanders


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188458 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-15 13:45:36 +00:00
Jack Carter
e2a9376b1b [Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi

Patch by Daniel Sanders


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188457 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-15 12:24:57 +00:00
Craig Topper
d36e1efa4b Revert r188449 as it turns out we're just missing the instructions that need the v16i32/v16f32 matching.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188454 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-15 08:38:25 +00:00
Hao Liu
d9767021f8 Clang and AArch64 backend patches to support shll/shl and vmovl instructions and ACLE functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188451 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-15 08:26:11 +00:00
Craig Topper
46ceaf4ba6 Don't let isPermImmMask handle v16i32 since VPERMI doesn't match on that type. Remove 128-bit vector handling from isPermImmMask too, it's covered by isPSHUFDMask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188449 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-15 07:30:51 +00:00
Tom Stellard
a41520cf9b R600/SI: Improve legalization of vector operations
This should fix hangs in the OpenCL piglit tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188431 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-14 23:25:00 +00:00
Tom Stellard
e8e33f448e R600/SI: Replace v1i32 type with i32 in imageload and sample intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188430 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-14 23:24:53 +00:00
Tom Stellard
68db37b952 R600/SI: Convert v16i8 resource descriptors to i128
Now that compute support is better on SI, we can't continue using v16i8
for descriptors since this is also a legal type in OpenCL.

This patch fixes numerous hangs with the piglit OpenCL test and since
we now use a target specific DAG node for LOAD_CONSTANT with the
correct MemOperandFlags, this should also fix:

https://bugs.freedesktop.org/show_bug.cgi?id=66805

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188429 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-14 23:24:45 +00:00
Tom Stellard
34f505e227 R600/SI: Use i8 types for resource descriptors in tests
We switched from i32 to i8 types a while ago and the tests were never
updated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188428 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-14 23:24:37 +00:00
Tom Stellard
38d5e1c36d R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2
Using REG_SEQUENCE for BUILD_VECTOR rather than a series of INSERT_SUBREG
instructions should make it easier for the register allocator to coalasce
unnecessary copies.

v2:
  - Use an SGPR register class if all the operands of BUILD_VECTOR are
    SGPRs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188427 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-14 23:24:32 +00:00
Tom Stellard
df4626ef15 R600/SI: Assign a register class to the $vaddr operand for MIMG instructions
The previous code declared the operand as unknown:$vaddr, which made
it possible for scalar registers to be used instead of vector registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188425 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-14 23:24:17 +00:00
Peter Collingbourne
f62372f6a3 DataFlowSanitizer: move abilist input file to Inputs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188423 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-14 22:28:36 +00:00
Tom Stellard
67ca7b1bb0 R600/SI: Handle MSAA texture targets
Patch by: Marek Olšák

Signed-off-by: Marek Olšák <marek.olsak@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188421 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-14 22:22:14 +00:00
Tom Stellard
a7b7ab3299 R600/SI: Allow conversion between v32i8 and v8i32
Patch by: Marek Olšák

Signed-off-by: Marek Olšák <marek.olsak@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188420 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-14 22:22:09 +00:00
Tom Stellard
2760387d86 R600/SI: Add pattern for fp_to_uint
This fixes the F2U opcode for the Mesa driver.

Patch by: Marek Olšák

Signed-off-by: Marek Olšák <marek.olsak@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188418 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-14 22:21:57 +00:00
Peter Collingbourne
ef8136dda1 DataFlowSanitizer: Instrumentation for memset.
Differential Revision: http://llvm-reviews.chandlerc.com/D1395

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188412 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-14 20:51:38 +00:00
Hal Finkel
341c1a50ad Actually fix PPC64 64-bit GPR inline asm constraint matching
This is a follow-up to r187693, correcting that code to request the correct
register class. The previous version, with the wrong register class, was not
really correcting the constraints, but rather was removing them. Coincidentally,
this fixed the failing test case in r187693, but obviously created other
problems.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188407 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-14 20:05:04 +00:00
Peter Collingbourne
fdb1a6c341 DataFlowSanitizer: greylist is now ABI list.
This replaces the old incomplete greylist functionality with an ABI
list, which can provide more detailed information about the ABI and
semantics of specific functions.  The pass treats every function in
the "uninstrumented" category in the ABI list file as conforming to
the "native" (i.e. unsanitized) ABI.  Unless the ABI list contains
additional categories for those functions, a call to one of those
functions will produce a warning message, as the labelling behaviour
of the function is unknown.  The other supported categories are
"functional", "discard" and "custom".

- "discard" -- This function does not write to (user-accessible) memory,
  and its return value is unlabelled.
- "functional" -- This function does not write to (user-accessible)
  memory, and the label of its return value is the union of the label of
  its arguments.
- "custom" -- Instead of calling the function, a custom wrapper __dfsw_F
  is called, where F is the name of the function.  This function may wrap
  the original function or provide its own implementation.

Differential Revision: http://llvm-reviews.chandlerc.com/D1345

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188402 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-14 18:54:12 +00:00
Alexey Samsonov
6889483ca4 llvm-symbolizer: add support for .gnu_debuglink section
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188386 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-14 17:09:30 +00:00
Renato Golin
dd34dc99fd Let t2LDRBi8 and t2LDRBi12 have same Base Pointer
When determining if two different loads are from the same base address,
this patch allows one load to use a t2LDRi8 address mode and another to
use a t2LDRi12 address mode. The current implementation is very
conservative and this allows the case of differing Thumb2 byte loads to
be considered. Allowing these differing modes instead of forcing the exact
same opcode is useful for situations where one opcodes loads from a base
address+1 and a second opcode loads for a base address-1.

Patch by Daniel Stewart.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188385 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-14 16:35:29 +00:00
Tim Northover
73cd0c844b Add test-case for hex floating-literals
Somehow I forgot to test one of the error conditions I'd added.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188372 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-14 14:55:54 +00:00
Tim Northover
337439d12d Support C99 hexadecimal floating-point literals in assembly
It's useful to be able to write down floating-point numbers without having to
worry about what they'll be rounded to (as C99 discovered), this extends that
ability to the MC assembly parsers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188370 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-14 14:23:31 +00:00
Akira Hatanaka
899ee589f5 [mips] Fix bug in parsing accumulator registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188344 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-14 01:15:52 +00:00
NAKAMURA Takumi
7cd85b7492 llvm/test/CodeGen/X86/setcc-sentinals.ll: Relax expressions for x86_64-win32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188340 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-14 00:46:00 +00:00
Matt Arsenault
fdc2660214 Fix always creating GEP with i32 indices
Use the pointer size if datalayout is available.
Use i64 if it's not, which is consistent with what other
places do when the pointer size is unknown.

The test doesn't really test this in a useful way
since it will be transformed to that later anyway,
but this now tests it for non-zero arrays and when
datalayout isn't available. The cases in
visitGetElementPtrInst should save an extra re-visit to
the newly created GEP since it won't need to cleanup after
itself.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188339 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-14 00:24:38 +00:00
Akira Hatanaka
bfb07b1054 [mips] Properly parse registers that appear in inline-asm constraints.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188336 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-14 00:21:25 +00:00
Hal Finkel
eaa8f5533f BBVectorize: Add initial stores to the write set when tracking uses
When computing the use set of a store, we need to add the store to the write
set prior to iterating over later instructions. Otherwise, if there is a later
aliasing load of that store, that load will not be tagged as a use, and bad
things will happen.

trackUsesOfI still adds later dependent stores of an instruction to that
instruction's write set, but it never sees the original instruction, and so
when tracking uses of a store, the store must be added to the write set by the
caller.

Fixes PR16834.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188329 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-13 23:34:32 +00:00
Nick Lewycky
fc2fc08b49 Remove duplicate copy of testcase in r188327.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188328 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-13 22:55:05 +00:00
Nick Lewycky
6c1fa7caae Revert r187191, which broke opt -mem2reg on the testcases included in PR16867.
However, opt -O2 doesn't run mem2reg directly so nobody noticed until r188146
when SROA started sending more things directly down the PromoteMemToReg path.

In order to revert r187191, I also revert dependent revisions r187296, r187322
and r188146. Fixes PR16867. Does not add the testcases from that PR, but both
of them should get added for both mem2reg and sroa when this revert gets
unreverted.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188327 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-13 22:51:58 +00:00
Jim Grosbach
51a0280d29 DAG: Combine (and (setne X, 0), (setne X, -1)) -> (setuge (add X, 1), 2)
A common idiom is to use zero and all-ones as sentinal values and to
check for both in a single conditional ("x != 0 && x != (unsigned)-1").
That generates code, for i32, like:
  testl %edi, %edi
  setne %al
  cmpl  $-1, %edi
  setne %cl
  andb  %al, %cl

With this transform, we generate the simpler:
  incl  %edi
  cmpl  $1, %edi
  seta  %al

Similar improvements for other integer sizes and on other platforms. In
general, combining the two setcc instructions into one is better.

rdar://14689217

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188315 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-13 21:30:58 +00:00
Jack Carter
da0860f78e [Mips] Support for unaligned load/store microMips instructions
This includes instructions lwl, lwr, swl and swr.

Patch by Zoran Jovnovic


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188312 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-13 20:19:16 +00:00
Carlo Kok
46f0b6f10a Output DW_AT_stmt_list dwarf debug info as DW_FORM_sec_offset instead of DW_FORM_data4 as it is a section offset (fixes the coff/dwarf debug info statement locations)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188297 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-13 17:46:57 +00:00
Joey Gouly
3f87f2510c ARMv8: SWP and SWPB are obsoleted on ARMv8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188288 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-13 16:40:47 +00:00
Mihai Popa
ea8ddd86b1 Fix signed overflow in when computing encodings for ADR instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188268 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-13 14:02:13 +00:00
Elena Demikhovsky
4d36bd80e6 AVX-512: Added CMP and BLEND instructions.
Lowering for SETCC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188265 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-13 13:24:07 +00:00
Evgeniy Stepanov
15ab9f4aaa Pass DIEHash::collectAttributes output argument by-pointer instead of by-value.
Before this, collectAttributes() was operating on a local object.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188254 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-13 07:57:01 +00:00
David Majnemer
6aa9315353 [-cxx-abi microsoft] Stick zero initialized symbols into the .bss section for COFF
Summary:
We need to do two things:

- Initialize BSSSection in MCObjectFileInfo::InitCOFFMCObjectFileInfo
- Teach TargetLoweringObjectFileCOFF::SelectSectionForGlobal what to do
  with it

This fixes PR16861.

Reviewers: rnk

Reviewed By: rnk

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1361

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188244 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-13 01:23:53 +00:00
Eric Christopher
0710bfa866 Add the start of DIE hashing for DWARF4 type units and split dwarf
CUs.

Currently only hashes the name of CUs and the names of any children,
but it's an obvious first step to show the framework. The testcase
should continue to be correct, however, as it's an empty TU.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188243 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-13 01:21:55 +00:00
Eric Christopher
b58bddf258 Add comment and source to testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188234 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-12 23:59:26 +00:00
Rui Ueyama
d9a84efe44 [FileCheck] Fix a bug that cause FileCheck to misidentify check-prefix
FileCheck should check to make sure the prefix was found, and not a word
containing it (e.g -check-prefix=BASEREL shouldn't match NOBASEREL).

Patch by Ron Ofir.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188221 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-12 23:05:59 +00:00
Kevin Enderby
ebc573ed5b Fix a crash with X86 Mach-O and a subtraction expression where both symbols are
undefined and produce an error message instead as this is a non-relocatable
expression with X86 Mach-O.

rdar://8920876


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188218 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-12 22:45:44 +00:00
Peter Collingbourne
4f96b7e147 Reapply r188119 now that the bug it exposed is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188217 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-12 22:38:43 +00:00