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262a96edb4
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1850 Commits

Author SHA1 Message Date
Evan Cheng
262a96edb4 Disable opt-ext pass to unbreak the build for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93286 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-13 01:51:43 +00:00
Jeffrey Yasskin
3aba5b1d60 Try to fix the ARM and PPC buildbots. The -mattr=vector-unaligned-mem 
flag doesn't exist there, and this is an x86 test.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93279 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-13 00:31:43 +00:00
Evan Cheng
7da9ecf967 Add a quick pass to optimize sign / zero extension instructions. For targets where the pre-extension values are available in the subreg of the result of the extension, replace the uses of the pre-extension value with the result + extract_subreg. 
For now, this pass is fairly conservative. It only perform the replacement when both the pre- and post- extension values are used in the block. It will miss cases where the post-extension values are live, but not used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93278 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-13 00:30:23 +00:00
Evan Cheng
d9d3a894b3 Add nounwind. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93244 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-12 18:29:23 +00:00
Duncan Sands
796248fdb1 Revert commit 93204, since it causes the assembler to barf 
on x86-64 linux with messages like this:
Error: Incorrect register `%r14' used with `l' suffix


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93242 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-12 17:46:16 +00:00
Dan Gohman
ad4f7a6882 Make several tests less fragile. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93230 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-12 04:52:47 +00:00
Dan Gohman
f1b4d26e67 Reapply the MOV64r0 patch, with a fix: MOV64r0 clobbers EFLAGS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93229 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-12 04:42:54 +00:00
Evan Cheng
b85071c736 Add manual ISD::OR fastisel selection routines. TableGen is no longer autogen them after 93152 and 93191. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93204 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 22:59:27 +00:00
Evan Cheng
199c4240fe Extend r93152 to work on OR r, r. If the source set bits are known not to overlap, then select as an ADD instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93191 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 22:03:29 +00:00
Chris Lattner
c31b0fc31f reduce this to a sensible testcase. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93189 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 21:58:19 +00:00
David Greene
67df1a1d64 Shorten up this testcase. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93187 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 21:50:35 +00:00
Evan Cheng
05920b8146 Revert 93158. It's breaking quite a few x86_64 tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93185 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 21:13:41 +00:00
Jakob Stoklund Olesen
dd437ba15e Avoid adding PHI arguments for a predecessor that has gone away when a BRCOND was constant folded. 
This fixes PR5980.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93184 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 21:02:33 +00:00
Dan Gohman
e5dacc55ad Use a 32-bit and with implicit zero-extension instead of a 64-bit and if it 
has an immediate with at least 32 bits of leading zeros, to avoid needing to
materialize that immediate in a register first.

FileCheckize, tidy, and extend a testcase to cover this case.

This fixes rdar://7527390.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93160 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 17:58:34 +00:00
Dan Gohman
71c25b7d7b Re-instate MOV64r0 and MOV16r0, with adjustments to work with the 
new AsmPrinter. This is perhaps less elegant than describing them
in terms of MOV32r0 and subreg operations, but it allows the
current register to rematerialize them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93158 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 17:37:57 +00:00
Dan Gohman
3e8e4fd40c Generalize this check to avoid depending on a specific register assignment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93157 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 17:24:27 +00:00
Dan Gohman
3bf224ba1d Make this test less trivial, to avoid spurious failures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93156 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 17:23:56 +00:00
Evan Cheng
4b0345be30 Select an OR with immediate as an ADD if the input bits are known zero. This allow the instruction to be 3address-fied if needed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93152 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 17:03:47 +00:00
David Greene
95eb2eeea6 Implement a feature (-vector-unaligned-mem) to allow targets to 
ignore alignment requirements for SIMD memory operands.  This
is useful on architectures like the AMD 10h that do not trap on
unaligned references if a status bit is twiddled at startup time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93151 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 16:29:42 +00:00
Jeffrey Yasskin
a77169dbeb Fix http://llvm.org/PR5729: x86-64 tail calls were putting their targets into 
R11, and then asserting that the target was in R9.  Since R9 isn't reserved for
the target anymore, and is used as an argument, this patch changes the
assertion.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93065 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-09 18:56:43 +00:00
Dan Gohman
d199636039 Revert an earlier change to SIGN_EXTEND_INREG for vectors. The VTSDNode 
really does need to be a vector type, because
TargetLowering::getOperationAction for SIGN_EXTEND_INREG uses that type,
and it needs to be able to distinguish between vectors and scalars.

Also, fix some more issues with legalization of vector casts.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93043 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-09 02:13:55 +00:00
Evan Cheng
306b4cafc1 Fix a critical bug in 64-bit atomic operation lowering for 32-bit. The results of the cmpxchg8b instructions are being thrown away when it branches back to the top of the checking loop. This means the loop always compares against the old value and this can result in a dead lock. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93028 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-08 23:41:50 +00:00
Evan Cheng
6f279e0bda ReplaceAllUsesOfValueWith may delete other nodes that the one being replaced. Do not delete dead nodes again. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92988 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-08 02:36:12 +00:00
Chris Lattner
bd1fccfad5 Fix rdar://7517201, a regression introduced by r92849. 
When folding a and(any_ext(load)) both the any_ext and the
load have to have only a single use.

This removes the anyext-uses.ll testcase which started failing
because it is unreduced and unclear what it is testing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92950 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-07 21:59:23 +00:00
Evan Cheng
17751dac3e Fix a minor regression from my dag combiner changes. One more place which needs to look pass truncates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92885 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-07 00:54:06 +00:00
Evan Cheng
d40d03e1bd Teach dag combine to fold the following transformation more aggressively: 
(OP (trunc x), (trunc y)) -> (trunc (OP x, y))

Unfortunately this simple change causes dag combine to infinite looping. The problem is the shrink demanded ops optimization tend to canonicalize expressions in the opposite manner. That is badness. This patch disable those optimizations in dag combine but instead it is done as a late pass in sdisel.

This also exposes some deficiencies in dag combine and x86 setcc / brcond lowering. Teach them to look pass ISD::TRUNCATE in various places.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92849 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-06 19:38:29 +00:00
Dan Gohman
d7d1a29003 Move this test from test/Transforms/IndVarSimplify to 
test/CodeGen/X86, as doesn't use -indvars, and it does use
llc -march=x86-64.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92799 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-05 22:52:54 +00:00
Bill Wendling
9f7c5c0dca Don't assign the shift the same type as the variable being shifted. This could 
result in illegal types for the SHL operator.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92797 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-05 22:39:10 +00:00
Dan Gohman
aceba31b7a Delete useless trailing semicolons. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92740 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-05 17:55:26 +00:00
Dan Gohman
c12e979790 Make this test more portable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92514 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-04 21:23:34 +00:00
Dan Gohman
b75e8642a6 Add some tests and update an existing test to reflect recent 
x86 isel peeps.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92509 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-04 20:53:54 +00:00
Chris Lattner
d0592d3be6 fix PR5930, allowing the asmprinter to emit difference between 
two labels as a truncate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92455 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-03 18:33:18 +00:00
Chris Lattner
2ef90d782e add PR# 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92451 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-03 18:10:58 +00:00
Chris Lattner
5099b31f98 differences between two blockaddress's don't cause a 
global variable initializer to require relocations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92450 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-03 18:09:40 +00:00
Chris Lattner
09987f73f6 allow this to work on linux hosts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92407 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-02 00:22:15 +00:00
Chris Lattner
133ce871df Teach codegen to handle: 
(X != null) | (Y != null) --> (X|Y) != 0
 (X == null) & (Y == null) --> (X|Y) == 0

so that instcombine can stop doing this for pointers.  This is part of PR3351,
which is a case where instcombine doing this for pointers (inserting ptrtoint)
is pessimizing code.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92406 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-02 00:00:03 +00:00
Chris Lattner
aac00392c3 rename file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92405 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-01 23:55:04 +00:00
Chris Lattner
f031e8ad01 Teach codegen to lower llvm.powi to an efficient (but not optimal) 
multiply sequence when the power is a constant integer.  Before, our
codegen for std::pow(.., int) always turned into a libcall, which was
really inefficient.

This should also make many gfortran programs happier I'd imagine.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92388 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-01 03:32:16 +00:00
Chris Lattner
04b091a782 handle equality memcmp of 8 bytes on x86-64 with two unaligned loads and a 
compare.  On other targets we end up with a call to memcmp because we don't
want 16 individual byte loads.  We should be able to use movups as well, but
we're failing to select the generated icmp.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92107 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-24 01:07:17 +00:00
Chris Lattner
8047d9a6be move an optimization for memcmp out of simplifylibcalls and into 
SDISel.  This optimization was causing simplifylibcalls to 
introduce type-unsafe nastiness.  This is the first step, I'll be 
expanding the memcmp optimizations shortly, covering things that
we really really wouldn't want simplifylibcalls to do.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92098 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-24 00:37:38 +00:00
Eric Christopher
d060b2576a Update objectsize intrinsic and associated dependencies. Fix 
lowering code and update testcases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91979 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-23 02:51:48 +00:00
Evan Cheng
b1f4981333 Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91910 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-22 17:47:23 +00:00
Evan Cheng
9ab2b98ba5 Increase opportunities to optimize (brcond (srl (and c1), c2)). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91717 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-18 21:31:31 +00:00
Evan Cheng
400073d546 On recent Intel u-arch's, folding loads into some unary SSE instructions can 
be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.

movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0

instead of
cvtss2sd (%rdi), %xmm0

An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91672 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-18 07:40:29 +00:00
Dan Gohman
f838e2366a Tidy up this testcase and add test for tailcall optimization 
with unreachable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91650 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-18 01:05:06 +00:00
Dan Gohman
f042396b0f Remove "tail" keywords. These calls are not intended to be tail calls. 
This protects this test from depending on codegen not performing the
tail call optimization by default.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91648 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-18 01:02:18 +00:00
Sean Callanan
108934c65d Instruction fixes, added instructions, and AsmString changes in the 
X86 instruction tables.

Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.

This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.

* X86*.td
	Removed tabs and fixed 80-line violations

* X86Instr64bit.td
	(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
		Added
	(CALL, CMOV) Added qualifiers
	(JMP) Added PC-relative jump instruction
	(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
		that it is 64-bit only (ambiguous since it has no
		REX prefix)
	(MOV) Added rr form going the other way, which is encoded
		differently
	(MOV) Changed immediates to offsets, which is more correct;
		also fixed MOV64o64a to have to a 64-bit offset
	(MOV) Fixed qualifiers
	(MOV) Added debug-register and condition-register moves
	(MOVZX) Added more forms
	(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
		(as with MOV) are encoded differently
	(ROL) Made REX.W required
	(BT) Uncommented mr form for disassembly only
	(CVT__2__) Added several missing non-intrinsic forms
	(LXADD, XCHG) Reordered operands to make more sense for
		MRMSrcMem
	(XCHG) Added register-to-register forms
	(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
	(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
		Added
* X86InstrFPStack.td
	(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
	 FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
	 FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
	 FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
	 FXRSTOR)
		Added
	(FCOM, FCOMP) Added qualifiers
	(FSTENV, FSAVE, FSTSW) Fixed opcode names
	(FNSTSW) Added implicit register operand
* X86InstrInfo.td
	(opaque512mem) Added for FXSAVE/FXRSTOR
	(offset8, offset16, offset32, offset64) Added for MOV
	(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
	 LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
	 LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
	 LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
	 CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
	 SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
	 VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
	 VMWRITE, VMXOFF, VMXON) Added
	(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
	(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
	 JGE, JLE, JG, JCXZ) Added 32-bit forms
	(MOV) Changed some immediate forms to offset forms
	(MOV) Added reversed reg-reg forms, which are encoded
		differently
	(MOV) Added debug-register and condition-register moves
	(CMOV) Added qualifiers
	(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
	(BT) Uncommented memory-register forms for disassembler
	(MOVSX, MOVZX) Added forms
	(XCHG, LXADD) Made operand order make sense for MRMSrcMem
	(XCHG) Added register-register forms
	(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
	(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
	change

* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
  qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-18 00:01:26 +00:00
Evan Cheng
2e489c4f9d Re-enable 91381 with fixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91489 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-16 00:53:11 +00:00
Dale Johannesen
fc49bd2447 Do better with physical reg operands (typically, from inline asm) 
in local register allocator.  If a reg-reg copy has a phys reg
input and a virt reg output, and this is the last use of the phys
reg, assign the phys reg to the virt reg.  If a reg-reg copy has
a phys reg output and we need to reload its spilled input, reload
it directly into the phys reg than passing it through another reg.

Following 76208, there is sometimes no dependency between the def of
a phys reg and its use; this creates a window where that phys reg
can be used for spilling (this is true in linear scan also).  This
is bad and needs to be fixed a better way, although 76208 works too
well in practice to be reverted.  However, there should normally be
no spilling within inline asm blocks.  The patch here goes a long way
towards making this actually be true.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91485 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-16 00:29:41 +00:00
Kenneth Uildriks
76df3f398c For fastcc on x86, let ECX be used as a return register after EAX and EDX 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91410 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-15 03:27:52 +00:00