Commit Graph

185 Commits

Author SHA1 Message Date
Rafael Espindola
7d7d99622f Replace PROLOG_LABEL with a new CFI_INSTRUCTION.
The old system was fairly convoluted:
* A temporary label was created.
* A single PROLOG_LABEL was created with it.
* A few MCCFIInstructions were created with the same label.

The semantics were that the cfi instructions were mapped to the PROLOG_LABEL
via the temporary label. The output position was that of the PROLOG_LABEL.
The temporary label itself was used only for doing the mapping.

The new CFI_INSTRUCTION has a 1:1 mapping to MCCFIInstructions and points to
one by holding an index into the CFI instructions of this function.

I did consider removing MMI.getFrameInstructions completelly and having
CFI_INSTRUCTION own a MCCFIInstruction, but MCCFIInstructions have non
trivial constructors and destructors and are somewhat big, so the this setup
is probably better.

The net result is that we don't create temporary labels that are never used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203204 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-07 06:08:31 +00:00
Craig Topper
49d687d58f Get rid of a vector copy by just making a pointer out of the reference returned by getInstructionsByEnumValue instead of assigning it to a new vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200828 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-05 07:56:49 +00:00
Roman Divacky
af43b47c5a Constant propagate MachineInstrClassName.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198969 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-10 22:59:49 +00:00
Rafael Espindola
dd86e54b61 All backends use MC now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198959 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-10 21:49:27 +00:00
Rafael Espindola
79a1166b13 Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196066 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-02 05:10:04 +00:00
Ahmed Bougacha
254ce94c26 TableGen: Refactor AsmWriterEmitter to keep AsmWriterInsts.
These used to be referenced by the CGI->AWI map (in AsmWriterEmitter), but
stored in a vector local to EmitPrintInstruction. Move the vector to
AsmWriterEmitter too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193525 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 18:07:17 +00:00
Rafael Espindola
8819c84aed Remove several unused variables.
Patch by Alp Toker.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191757 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 13:32:03 +00:00
Benjamin Kramer
209a8c8e35 llvm-tblgen: Mangle operand replacements into the strings in printAliasInstr.
Cuts down the bloat in the AArch64 asm writer a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190527 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-11 15:42:16 +00:00
Jack Carter
37ef65b9c1 This patch that sets the EmitAlias flag in td files
and enables the instruction printer to print aliased 
instructions. 

Due to usage of RegisterOperands a change in common 
code (utils/TableGen/AsmWriterEmitter.cpp) is required 
to get the correct register value if it is a RegisterOperand.

Contributer: Vladimir Medic
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174358 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05 08:32:10 +00:00
Tim Northover
7bf2e1b9ef Check whether MCInst operand isImm before calling getImm.
When processing possible aliases, TableGen assumes that if an operand *can* be
an immediate, then it always *will* be. This is incorrect for the AArch64
backend. This patch inserts a check in the generated code to make sure isImm is
true first.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171972 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09 13:32:04 +00:00
Joerg Sonnenberger
61131ab15f Remove exception handling usage from tblgen.
Most places can use PrintFatalError as the unwinding mechanism was not
used for anything other than printing the error. The single exception
was CodeGenDAGPatterns.cpp, where intermediate errors during type
resolution were ignored to simplify incremental platform development.
This use is replaced by an error flag in TreePattern and bailout earlier
in various places if it is set. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166712 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25 20:33:17 +00:00
Sean Silva
3f7b7f8ce0 tblgen: Use semantically correct RTTI functions.
Also, some minor cleanup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165647 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10 20:24:47 +00:00
Sean Silva
6cfc806a6b tblgen: Mechanically move dynamic_cast<> to dyn_cast<>.
Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>.
That will happen in a future patch.

There are also two dyn_cast_or_null<>'s slipped in instead of
dyn_cast<>'s, since they were causing crashes with just dyn_cast<>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165646 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10 20:24:43 +00:00
Craig Topper
5974c31acb Revert r163878 as it breaks on targets with alternate register names. Such targets do not exist in the main tree so this was not noticed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163959 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-15 01:22:42 +00:00
Craig Topper
f4d78241ea Allow the second opcode info table to be 8, 16, or 32-bits as needed to represent additional fragments. This recovers some space on ATT X86 syntax and PowerPC which only need 40-bits instead of 48-bits. This also increases ARM to 64-bits to fully encode all of its operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163880 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-14 08:33:11 +00:00
Craig Topper
4e5babe4f3 Reduce size of register name index tables by using uint16_t for all in tree targets. If more than 16-bits are needed for any out of tree targets, code will detect and use uint32_t instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163878 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-14 06:37:49 +00:00
Manman Ren
785a41d138 AsmWriterEmitter: OpInfo2 should be unsigned 16-bit.
Fix an issue in r163814.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163837 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-13 20:47:48 +00:00
Manman Ren
6579cf8df6 AsmWriterEmitter: increase the number of bits for OpcodeInfo from 32-bit to
48-bit if necessary, in order to reduce the generated code size.

We have 900 cases not covered by OpcodeInfo in ATT AsmWriter and more in Intel
AsmWriter and ARM AsmWriter.

This patch reduced the clang Release build size by 50k, running on a Mac Pro.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163814 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-13 17:43:46 +00:00
Craig Topper
f553587a4f Clean up includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160852 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-27 06:44:02 +00:00
Jakob Stoklund Olesen
6f36fa981a Write llvm-tblgen backends as functions instead of sub-classes.
The TableGenBackend base class doesn't do much, and will be removed
completely soon.

Patch by Sean Silva!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158311 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-11 15:37:55 +00:00
Jim Grosbach
b4b26f87fe Revert "Replace some uses of std:map<std::string,...> with StringMap."
StringMap iterators are not deterministic, and that's more important
here than speed or memory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155039 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 20:24:49 +00:00
Jim Grosbach
325478d78d Replace some uses of std:map<std::string,...> with StringMap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155037 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 19:13:59 +00:00
Jim Grosbach
a5b0685142 Use SmallVector for the requirements on an InstAlias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155034 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 19:02:43 +00:00
Jim Grosbach
016c679c50 Tidy up. Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155032 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 18:56:33 +00:00
Craig Topper
58609b7413 Convert assert(false) followed by a return to llvm_unreachable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153997 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-04 04:55:46 +00:00
Craig Topper
9b1b25f063 Tidy up spacing in some tablegen outputs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153937 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03 06:52:47 +00:00
Benjamin Kramer
94338594ef Emit the asm writer's mnemonic table with SequenceToOffsetTable.
This way we can get AVX v-prefixed instructions tail merged with the normal insns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153869 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02 09:13:46 +00:00
Craig Topper
7c0b3c1fb6 Remove getInstructionName from MCInstPrinter implementations in favor of using the instruction name table from MCInstrInfo. Reduces static data in the InstPrinter implementations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153863 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02 07:01:04 +00:00
Craig Topper
a4bd58b0f0 Use SequenceToOffsetTable to generate instruction name table for AsmWriter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153857 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02 00:47:39 +00:00
Benjamin Kramer
cef670a3a3 Rip out emission of the regIsInRegClass function for the asm printer.
It's slow, bloated and completely redundant with MCRegisterClass::contains.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153782 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 23:13:40 +00:00
Jakob Stoklund Olesen
c19f72bd83 Use SequenceToOffsetTable in emitRegisterNameString.
This allows suffix sharing in register names. (AX is a suffix of EAX).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153777 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 21:12:52 +00:00
Jakob Stoklund Olesen
bcfa982c48 Revert r152202: "Use uint16_t to store InstrNameIndices in MCInstrInfo."
We cannot limit the concatenated instruction names to 64K.  ARM is
already at 32K, and it is easy to imagine a target with more
instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152817 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15 18:05:57 +00:00
Jakob Stoklund Olesen
d66b9a222b Revert r152105: "Use uint16_t to store indices into string table"
This patch limited the concatenated register names to 64K which meant
that the total number of registers was many times less than 64K.

If any compilers actually enforce the 64K limit on string literals, and
it turns out to be a problem, we should fix that problem by not using
long string literals.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152816 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15 18:05:54 +00:00
Craig Topper
88d2fa438a Re-commit r152202 hopefully fixing the MSVC linker error.
Original commit message:
Use uint16_t to store InstrNameIndices in MCInstrInfo. Add asserts to protect all 16-bit string table offsets. Also make sure the string to offset table string is not larger than 65536 characters since larger string literals aren't portable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152296 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-08 06:55:27 +00:00
Chad Rosier
3c777947f4 Revert r152202 as it's causing internal buildbot failures.
Original commit message:
Use uint16_t to store InstrNameIndices in MCInstrInfo. Add asserts to protect 
all 16-bit string table offsets. Also make sure the string to offset table 
string is not larger than 65536 characters since larger string literals aren't 
portable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152233 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 17:06:40 +00:00
Craig Topper
d3c9d9447e Use uint16_t to store InstrNameIndices in MCInstrInfo. Add asserts to protect all 16-bit string table offsets. Also make sure the string to offset table string is not larger than 65536 characters since larger string literals aren't portable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152202 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 05:17:23 +00:00
Craig Topper
f0c094b115 Use uint16_t to store indices into string table since C++ only allows 64K string literals so the index into the big string can never be larger than that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152105 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 06:04:39 +00:00
Craig Topper
655b8de7b2 Convert assert(0) to llvm_unreachable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149814 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05 07:21:30 +00:00
David Blaikie
2bd335470f Remove unnecessary default cases in switches that cover all enum values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147855 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10 16:47:17 +00:00
Jim Grosbach
bfc9429c2b ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions.
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144606 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 01:46:57 +00:00
Jakob Stoklund Olesen
6fea31e730 TableGen: Privatize CodeGenRegisterClass::TheDef and Name.
When TableGen starts creating its own register classes, the synthesized
classes won't have a Record reference.  All register classes must have a
name, though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141081 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 15:28:08 +00:00
Peter Collingbourne
7c78888887 Move TableGen's parser and entry point into a library
This is the first step towards splitting LLVM and Clang's tblgen executables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140951 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 16:41:13 +00:00
Jakob Stoklund Olesen
29f018cee6 Switch to ArrayRef<CodeGenRegisterClass*>.
This makes it possible to allocate CodeGenRegisterClass instances
dynamically and reorder them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140816 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 22:28:37 +00:00
Evan Cheng
68ae5b4bea Remove the AsmWriterEmitter (unused) feature that rely on TargetSubtargetInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134457 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 02:02:33 +00:00
Francois Pichet
2e10b08744 Change AsmName's type from StringRef to std::string. AsmName was pointing to a temporary string object that was destroyed. This is undefined behavior and MSVC didn't like it.
This fixes over 300+ failing tests on MSVC.
Credit for this fix goes to chapuni.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134064 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29 11:25:34 +00:00
Owen Anderson
bea6f615ee Add support for alternative register names, useful for instructions whose operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0.
Patch by Jim Grosbach.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133940 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27 21:06:21 +00:00
Jim Grosbach
0b6a44afb9 Consolidate some TableGen diagnostic helper functions.
TableGen had diagnostic printers sprinkled about in a few places. Pull them
together into a single location in Error.cpp.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133568 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-21 22:55:50 +00:00
Jakob Stoklund Olesen
abdbc84b4e Store CodeGenRegisters as pointers so they won't be reallocated.
Reuse the CodeGenRegBank DenseMap in a few places that would build their
own or use linear search.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133333 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-18 04:26:06 +00:00
Jakob Stoklund Olesen
ae1920b1ef Give CodeGenRegisterClass a real sorted member set.
Make the Elements vector private and expose an ArrayRef through
getOrder() instead. getOrder will eventually provide multiple
user-specified allocation orders.

Use the sorted member set for member and subclass tests. Clean up a lot
of ad hoc searches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133040 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15 04:50:36 +00:00
Bill Wendling
393c4047c0 Improve the heuristic to emit the alias if the number of hard-coded registers
are also greater than the alias.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133038 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15 04:31:19 +00:00