Commit Graph

3407 Commits

Author SHA1 Message Date
Mon P Wang
2887310630 Added MemOperands to Atomic operations since Atomics touches memory.
Added abstract class MemSDNode for any Node that have an associated MemOperand
Changed atomic.lcs => atomic.cmp.swap, atomic.las => atomic.load.add, and
atomic.lss => atomic.load.sub


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52706 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-25 08:15:39 +00:00
Evan Cheng
601ca4b434 Enable two-address remat by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52701 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-25 01:16:38 +00:00
Dale Johannesen
a68f9013f2 Add v2f32 (MMX) type to X86. Support is primitive:
load,store,call,return,bitcast.  This is enough to
make call and return work.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52691 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-24 22:01:44 +00:00
Evan Cheng
9ef4ca2e81 If it's determined safe, remat MOV32r0 (i.e. xor r, r) and others as it is instead of using the longer MOV32ri instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52670 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-24 07:10:51 +00:00
Dan Gohman
2d0d59380a Add a note about a potential PIC optimization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52663 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-24 00:53:07 +00:00
Dan Gohman
db7991de75 Fixes for being compiled PIC on Linux. This isn't the most
general solution possible, but it's a fairly simple one.
Based on a patch from the OpenGTL project!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52662 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-24 00:50:01 +00:00
Dan Gohman
09d3fdc254 Remove unnecessary #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52613 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-22 19:21:26 +00:00
Eli Friedman
2c8e64d3e4 Fix a bug with <8 x i16> shuffle lowering on X86 where parts of the
shuffle could be skipped.  The check is invalid because the loop index i 
doesn't correspond to the element actually inserted. The correct check is
already done a few lines earlier, for whether the element is already in 
the right spot, so this shouldn't have any effect on the codegen for 
code that was already correct.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52486 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-19 06:09:51 +00:00
Evan Cheng
359e9371b9 XOR32rr, etc. are not AsCheapAsMove, but MOV32ri, etc. are.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52454 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-18 08:13:07 +00:00
Evan Cheng
fab8387384 Unbreak DECLARE isel in pic mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52439 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-18 02:48:27 +00:00
Evan Cheng
851bc04533 Rather than avoiding to wrap ISD::DECLARE GV operand in X86ISD::Wrapper, simply handle it at dagisel time with x86 specific isel code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52377 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-17 02:01:22 +00:00
Evan Cheng
4e444436f2 Horizontal-add instructions are not commutative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52363 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 21:16:24 +00:00
Evan Cheng
35b9a7790e mpsadbw is commutable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52352 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:25:59 +00:00
Evan Cheng
58dcb0e0cd Add option to commuteInstruction() which forces it to create a new (commuted) instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52308 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 07:33:11 +00:00
Andrew Lenharth
507a58ac9b add missing atomic intrinsic from gcc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52270 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-14 05:48:15 +00:00
Duncan Sands
d4b9c17fb7 Disable some DAG combiner optimizations that may be
wrong for volatile loads and stores.  In fact this
is almost all of them!  There are three types of
problems: (1) it is wrong to change the width of
a volatile memory access.  These may be used to
do memory mapped i/o, in which case a load can have
an effect even if the result is not used.  Consider
loading an i32 but only using the lower 8 bits.  It
is wrong to change this into a load of an i8, because
you are no longer tickling the other three bytes.  It
is also unwise to make a load/store wider.  For
example, changing an i16 load into an i32 load is
wrong no matter how aligned things are, since the
fact of loading an additional 2 bytes can have
i/o side-effects.  (2) it is wrong to change the
number of volatile load/stores: they may be counted
by the hardware.  (3) it is wrong to change a volatile
load/store that requires one memory access into one
that requires several.  For example on x86-32, you
can store a double in one processor operation, but to
store an i64 requires two (two i32 stores).  In a
multi-threaded program you may want to bitcast an i64
to a double and store as a double because that will
occur atomically, and be indivisible to other threads.
So it would be wrong to convert the store-of-double
into a store of an i64, because this will become two
i32 stores - no longer atomic.  My policy here is
to say that the number of processor operations for
an illegal operation is undefined.  So it is alright
to change a store of an i64 (requires at least two
stores; but could be validly lowered to memcpy for
example) into a store of double (one processor op).
In short, if the new store is legal and has the same
size then I say that the transform is ok.  It would
also be possible to say that transforms are always
ok if before they were illegal, whether after they
are illegal or not, but that's more awkward to do
and I doubt it buys us anything much.
However this exposed an interesting thing - on x86-32
a store of i64 is considered legal!  That is because
operations are marked legal by default, regardless of
whether the type is legal or not.  In some ways this
is clever: before type legalization this means that
operations on illegal types are considered legal;
after type legalization there are no illegal types
so now operations are only legal if they really are.
But I consider this to be too cunning for mere mortals.
Better to do things explicitly by testing AfterLegalize.
So I have changed things so that operations with illegal
types are considered illegal - indeed they can never
map to a machine operation.  However this means that
the DAG combiner is more conservative because before
it was "accidentally" performing transforms where the
type was illegal because the operation was nonetheless
marked legal.  So in a few such places I added a check
on AfterLegalize, which I suppose was actually just
forgotten before.  This causes the DAG combiner to do
slightly more than it used to, which resulted in the X86
backend blowing up because it got a slightly surprising
node it wasn't expecting, so I tweaked it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52254 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-13 19:07:40 +00:00
Anton Korobeynikov
096b461b2e Properly lower DYNAMIC_STACKALLOC - bracket all black magic with
CALLSEQ_BEGIN & CALLSEQ_END.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52225 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-11 20:16:42 +00:00
Rafael Espindola
d674b4e87d add support for PIC on linux x86-64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52139 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-09 09:52:31 +00:00
Duncan Sands
8e4eb09b1e Remove comparison methods for MVT. The main cause
of apint codegen failure is the DAG combiner doing
the wrong thing because it was comparing MVT's using
< rather than comparing the number of bits.  Removing
the < method makes this mistake impossible to commit.
Instead, add helper methods for comparing bits and use
them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52098 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-08 20:54:56 +00:00
Duncan Sands
83ec4b6711 Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction.  Rename the type
to MVT.  To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits().  Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-06 12:08:01 +00:00
Evan Cheng
1b022cf688 Don't break strict aliasing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52026 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-05 22:59:21 +00:00
Dale Johannesen
428ac54894 Add StringConstantPrefix to control what the
assembler names of string constants look like.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51909 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-03 18:09:06 +00:00
Rafael Espindola
da5860fa8b Don't use the GOT for symbols that are not externally visible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51865 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-02 07:52:43 +00:00
Dan Gohman
e4c67cdab4 Teach the DAGISelEmitter to not compute the variable_ops operand
index for the input pattern in terms of the output pattern. Instead
keep track of how many fixed operands the input pattern actually
has, and have the input matching code pass the output-emitting
function that index value. This simplifies the code, disentangles
variables_ops from the support for predication operations, and
makes variable_ops more robust.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51808 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-31 02:11:25 +00:00
Bill Wendling
37a6134165 Add the "AsCheapAsAMove" flag to some 64-bit xor instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51761 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-30 06:47:04 +00:00
Dan Gohman
b4106170dd Add patterns for CALL32m and CALL64m. They aren't matched in most
cases due to an isel deficiency already noted in
lib/Target/X86/README.txt, but they can be matched in this fold-call.ll
testcase, for example.

This is interesting mainly because it exposes a tricky tblgen bug;
tblgen was incorrectly computing the starting index for variable_ops
in the case of a complex pattern.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51706 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-29 21:50:34 +00:00
Dan Gohman
d35121ad00 Fix a tblgen problem handling variable_ops in tblgen instruction
definitions. This adds a new construct, "discard", for indicating
that a named node in the input matching pattern is to be discarded,
instead of corresponding to a node in the output pattern. This
allows tblgen to know where the arguments for the varaible_ops are
supposed to begin.

This fixes "rdar://5791600", whatever that is ;-).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51699 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-29 19:57:41 +00:00
Dan Gohman
21323f3a82 Expand small memmovs using inline code. Set the X86 threshold for expanding
memmove to a more plausible value, now that it's actually being used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51696 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-29 19:42:22 +00:00
Evan Cheng
f26ffe987c Implement vector shift up / down and insert zero with ps{rl}lq / ps{rl}ldq.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51667 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-29 08:22:04 +00:00
Bill Wendling
75cf88f1fe XOR?RI instructions aren't as cheap as moves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51664 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-29 03:46:36 +00:00
Bill Wendling
bd0879d7d9 Implement "AsCheapAsAMove" for some obviously cheap instructions: xor and the
like.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51662 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-29 01:02:09 +00:00
Dan Gohman
c2ecdc5a26 Fix the encoding for two more "rm" instructions that were using MRMSrcReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51630 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-28 01:50:19 +00:00
Mon P Wang
bfbbd4d221 Fixed X86 encoding error CVTPS2PD and CVTPD2PS when the source operand
is a memory location


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51626 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-28 00:42:27 +00:00
Nate Begeman
f7333bf4a2 Don't attempt to create VZEXT_LOAD out of an extload. This an issue where the
code generator would do something like this:

f64 = load f32 <anyext>, f32mem
v2f64 = insertelt undef, %0, 0
v2f64 = insertelt %1, 0.0, 1

into 

v2f64 = vzext_load f32mem

which on x86 is movsd, when you really wanted a cvtss2sd/movsd pair.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51624 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-28 00:24:25 +00:00
Evan Cheng
a31593901d Eliminate x86.sse2.punpckh.qdq and x86.sse2.punpckl.qdq.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51533 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-24 02:56:30 +00:00
Evan Cheng
e716bb1c59 Eliminate x86.sse2.movs.d, x86.sse2.shuf.pd, x86.sse2.unpckh.pd, and x86.sse2.unpckl.pd intrinsics. These will be lowered into shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51531 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-24 02:14:05 +00:00
Evan Cheng
fe5b159ae2 This is done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51526 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-24 00:10:13 +00:00
Evan Cheng
999dbe6bbc Remove x86.sse2.loadh.pd and x86.sse2.loadl.pd. These will be lowered into load and shuffle instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51522 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-24 00:07:29 +00:00
Evan Cheng
cd0baf21a1 Use movlps / movhps to modify low / high half of 16-byet memory location.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51501 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-23 21:23:16 +00:00
Dan Gohman
a9e75631a7 Elaborate on the entry on integer vector multiplication by constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51491 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-23 18:05:39 +00:00
Evan Cheng
50f778deed Fix a duplicated pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51490 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-23 18:00:18 +00:00
Dan Gohman
0b924dcef8 Use PMULDQ for v2i64 multiplies when SSE4.1 is available. And add
load-folding table entries for PMULDQ and PMULLD.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51489 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-23 17:49:40 +00:00
Evan Cheng
d4083d01d2 New entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51487 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-23 17:28:11 +00:00
Chris Lattner
3adaa93700 we compile multiply-by-constant into horrible code. Doesn't sse4 have some
instruction for doing this?


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51473 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-23 04:29:53 +00:00
Evan Cheng
b1938263c7 Bug: rcpps can only folds a load if the address is 16-byte aligned. Fixed many 'ps' load folding patterns in X86InstrSSE.td which are missing the proper alignment checks.
Also fixed some 80 col. violations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51462 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-23 00:37:07 +00:00
Dale Johannesen
bbcb34cafb Put const weak stuff in appropriate section on Darwin.
g++.dg/abi/key2.C



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51458 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-23 00:16:59 +00:00
Evan Cheng
5bbaf01b84 X86CodeEmitter should not set PIC style to None at initialization time. This will break codegen if relocation model is changed to PIC_ later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51455 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-22 23:55:24 +00:00
Evan Cheng
c36c0ab44b Add missing patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51435 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-22 18:56:56 +00:00
Evan Cheng
8e8de684c7 movsd and movq do not require 16-byte alignment. This fixes vec_set-5.ll on Linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51327 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-20 18:24:47 +00:00
Evan Cheng
a125e62117 runOnMachineFunction should set IsPIC because relocation model may have been changed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51291 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-20 01:56:59 +00:00