6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-24 06:30:19 +00:00
Code Issues Projects Releases Wiki Activity
37,746 Commits 39 Branches 0 Tags 277 MiB
2974e49019
Commit Graph

4860 Commits

Author SHA1 Message Date
Bill Wendling
2974e49019 Temporarily revert r48491. It's breaking test/CodeGen/X86/xorl.ll. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48510 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-18 22:29:51 +00:00
Dale Johannesen
cf49819877 Make conversions of i8/i16 to ppcf128 work. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48493 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-18 17:28:38 +00:00
Christopher Lamb
981576c818 Target independent DAG transform to use truncate for field extraction + sign extend on targets where this is profitable. Passes nightly on x86-64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48491 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-18 16:46:39 +00:00
Evan Cheng
3c88d742d4 Rewrite code that propagate isDead information after a dead copy is coalesced. This remove some ugly spaghetti code and fixed a number of subtle bugs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48490 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-18 08:26:47 +00:00
Owen Anderson
755ebab37d A first attempt at updating live intervals, with code lifted from 
the coalescer.  This doesn't really work, but gets us farther than
before.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48446 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-17 06:08:26 +00:00
Christopher Lamb
c929823525 Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48412 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-16 03:12:01 +00:00
Evan Cheng
20ccded7de Remove isImplicitDef TargetInstrDesc flag. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48381 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-15 00:19:36 +00:00
Evan Cheng
da47e6e0d0 Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48380 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-15 00:03:38 +00:00
Duncan Sands
23a1d0c161 Do not generate special entries in the dwarf eh 
table for nounwind calls.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48373 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-14 21:36:24 +00:00
Evan Cheng
c17ba8a28d Fix PR2138. Apparently any modification to a std::multimap (including remove entries for a different key) can invalidate multimap iterators. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48371 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-14 20:44:01 +00:00
Duncan Sands
d1ba3338d1 Simplify using getIntPtrConstant. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48355 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-14 05:23:57 +00:00
Nate Begeman
5922f561c6 Tabs -> spaces 
Use getIntPtrConstant in a couple places to shorten stuff up
Handle splitting vector shuffles with undefs in the mask


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48351 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-14 00:53:31 +00:00
Evan Cheng
db2d773fe6 Livein copy scheduling fixes: do not coalesce physical register copies, correctly determine the safe location to insert the copies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48348 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-14 00:14:55 +00:00
Dan Gohman
002e5d0a17 More APInt-ification. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48344 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-13 22:13:53 +00:00
Evan Cheng
c438f35df9 Undo tweak. It had no obvious benefit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48341 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-13 17:42:48 +00:00
Evan Cheng
a2248682ae Typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48337 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-13 08:04:35 +00:00
Evan Cheng
0099ae2468 Don't try to sink 3-address instruction if convertToThreeAddress created more than one instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48336 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-13 07:56:58 +00:00
Evan Cheng
f3ff6992a3 Remove an unused command line option. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48334 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-13 06:38:28 +00:00
Evan Cheng
875357d213 TwoAddressInstructionPass enhancement. After it converts a two address instruction into a 3-address one, sink it past the instruction that kills the read-mod-write register if its definition is used past the kill. This reduces the number of live register by one. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48333 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-13 06:37:55 +00:00
Christopher Lamb
6634e26aa1 Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects. 
Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48329 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-13 05:47:01 +00:00
Evan Cheng
1c9b8cf28c Remove unused options. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48319 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-13 02:41:34 +00:00
Evan Cheng
b27087f5aa Refactor some code out of MachineSink into a MachineInstr query. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48311 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-13 00:44:09 +00:00
Evan Cheng
9e23336d0c Experimental scheduler change to schedule / coalesce the copies added for function livein's. Take 2008-03-10-RegAllocInfLoop.ll, the schedule looks like this after these copies are inserted: 
entry: 0x12049d0, LLVM BB @0x1201fd0, ID#0:
Live Ins: %EAX %EDX %ECX
        %reg1031<def> = MOVPC32r 0
        %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def>
        %reg1028<def> = MOV32rr %EAX
        %reg1029<def> = MOV32rr %EDX
        %reg1030<def> = MOV32rr %ECX
        %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x1201910 + 0]
        %reg1025<def> = MOV32rr %reg1029
        %reg1026<def> = MOV32rr %reg1030
        %reg1024<def> = MOV32rr %reg1028

The copies unnecessarily increase register pressure and it will end up requiring a physical register to be spilled.

With -schedule-livein-copies:
entry: 0x12049d0, LLVM BB @0x1201fa0, ID#0:
Live Ins: %EAX %EDX %ECX
        %reg1031<def> = MOVPC32r 0
        %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def>
        %reg1024<def> = MOV32rr %EAX
        %reg1025<def> = MOV32rr %EDX
        %reg1026<def> = MOV32rr %ECX
        %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x12018e0 + 0]

Much better!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48307 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-12 22:19:41 +00:00
Duncan Sands
d8742eeb2f Initial soft-float support for LegalizeTypes. I rewrote 
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit...  I also generalized it to work for
any sized floating point types, and removed the bogosity:
  SDOperand Mask1 = (SrcVT == MVT::f64)
    ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
    : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
  Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant!  So I just
generate this integer constant directly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-12 21:27:04 +00:00
Dan Gohman
b576931ca2 Change VirtRegMap's dump to dump to cerr, not DOUT, so that it 
can be called from within a debuger without having -debug specified
on the command-line.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48298 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-12 20:52:10 +00:00
Dan Gohman
39e33acf0a Fix typos in comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48297 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-12 20:50:04 +00:00
Duncan Sands
87a8615015 Fix typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48295 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-12 20:35:19 +00:00
Duncan Sands
25eb043759 Don't try to extract an i32 from an f64. This 
getCopyToParts problem was noticed by the new
LegalizeTypes infrastructure.  In order to avoid
this kind of thing in the future I've added a
check that EXTRACT_ELEMENT is only used with
integers.  Once LegalizeTypes is up and running
most likely BUILD_PAIR and EXTRACT_ELEMENT can
be removed, in favour of using apints instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48294 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-12 20:30:08 +00:00
Evan Cheng
c8e3b147ee Clean up my own mess. 
X86 lowering normalize vector 0 to v4i32. However DAGCombine can fold (sub x, x) -> 0 after legalization. It can create a zero vector of a type that's not expected (e.g. v8i16). We don't want to disable the optimization since leaving a (sub x, x) is really bad. Add isel patterns for other types of vector 0 to ensure correctness. It's highly unlikely to happen other than in bugpoint reduced test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48279 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-12 07:02:50 +00:00
Owen Anderson
dfd07eab24 We also need to collect the VN IDs for the PHI instructions for later updating. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48278 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-12 04:22:57 +00:00
Owen Anderson
0031671b41 When we're determining what registers to coallesce, track the VNInfo IDs for the definitions that 
feed the PHI instructions.  We'll need these IDs in order to update LiveIntervals properly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48277 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-12 03:13:29 +00:00
Evan Cheng
0cec956d81 Total brain cramp. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48274 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-12 02:05:05 +00:00
Evan Cheng
17d5f5496c Set NextMII after issuing a physical register spill. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48263 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-12 00:14:07 +00:00
Evan Cheng
4191b96f41 Minor debug output bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48261 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-12 00:02:46 +00:00
Anton Korobeynikov
4d86e2a6b8 Correctly propagate thread-local flag from aliasee to alias. This fixes PR2137 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48257 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 22:38:53 +00:00
Dan Gohman
bfae83139d Use PassManagerBase instead of FunctionPassManager for functions 
that merely add passes. This allows them to be used with either
FunctionPassManager or PassManager, or even with a custom new
kind of pass manager.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48256 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 22:29:46 +00:00
Anton Korobeynikov
22c9e65643 Honour aliases visibility during asm emission 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48249 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 21:41:14 +00:00
Evan Cheng
c1f53c7426 Transfer physical register spill info when load / store folding happens. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48246 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 21:34:46 +00:00
Dan Gohman
9736028d84 Use the correct value for InSignBit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48245 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 21:29:43 +00:00
Dan Gohman
ef5d194aaa Initial codegen support for functions and calls with multiple return values. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48244 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 21:11:25 +00:00
Christopher Lamb
1fab4a6bbb Recommitting parts of r48130. These do not appear to cause the observed failures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48223 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 10:09:17 +00:00
Evan Cheng
ea2378138f Use TargetRegisterInfo::getPhysicalRegisterRegClass. Remove duplicated code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48221 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 07:55:13 +00:00
Evan Cheng
676dd7c80b When the register allocator runs out of registers, spill a physical register around the def's and use's of the interval being allocated to make it possible for the interval to target a register and spill it right away and restore a register for uses. This likely generates terrible code but is before than aborting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48218 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 07:19:34 +00:00
Duncan Sands
ac7613a326 Some LegalizeTypes code factorization and minor 
enhancements.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48215 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 06:41:14 +00:00
Chris Lattner
5d03f21744 compile: double test() {} 
into:

_test:
	fldz
	ret

instead of:

_test:
	subl	$12, %esp
	#IMPLICIT_DEF %xmm0
	movsd	%xmm0, (%esp)
	fldl	(%esp)
	addl	$12, %esp
	ret



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48213 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 06:21:08 +00:00
Chris Lattner
c5733ac5d3 variadic instructions don't have operand info for variadic arguments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48208 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 03:14:42 +00:00
Dan Gohman
034f60ed24 Generalize ExpandIntToFP to handle the case where the operand is legal 
and it's the result that requires expansion. This code is a little confusing
because the TargetLoweringInfo tables for [US]INT_TO_FP use the operand type
(the integer type) rather than the result type. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48206 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 01:59:03 +00:00
Chris Lattner
b779580100 If a register operand comes from the variadic part of a node, don't 
verify the register constraint matches what the instruction expects.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48205 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 00:59:28 +00:00
Evan Cheng
524f961742 Temporarily revert 48175. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48204 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 00:27:34 +00:00
Dan Gohman
6cf9b8adf4 More APInt-ification. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48201 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 00:11:06 +00:00