Single and FP double reg types (which share the same reg class).
Now all methods marking/finding unused regs consider the regType
within the reg class, and SparcFloatRegClass specializes this code.
(2) Remove machine-specific regalloc. methods that are no longer needed.
In particular, arguments and return value from a call do not need
machine-specific code for allocation.
(3) Rename TargetRegInfo::getRegType variants to avoid unintentional
overloading when an include file is omitted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7334 91177308-0d34-0410-b5e6-96231b3b80d8
causing a nasty array bound error later.
2. Fix silly typo causing logical shift of unsigned long to use
SRL instead of SRLX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7330 91177308-0d34-0410-b5e6-96231b3b80d8
info (since multiple reg types may share the same reg class).
(2) Remove machine-specific regalloc. methods that are no longer needed.
In particular, arguments and return value from a call do not need
machine-specific code for allocation.
(3) Rename TargetRegInfo::getRegType variants to avoid unintentional
overloading when an include file is omitted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7329 91177308-0d34-0410-b5e6-96231b3b80d8
found to consider regType info (since multiple reg types may share
the same reg class, e.g., single and double on Sparc).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7327 91177308-0d34-0410-b5e6-96231b3b80d8
SlotCalculator in CWriter. (Unfortunately, all this means a lot of
X86/Printer's methods have to be de-constified again. Oh well.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7299 91177308-0d34-0410-b5e6-96231b3b80d8
doFinalization too except that would have made them shadow, not override,
the parent class :-P.
Allow *any* constant cast expression between pointers and longs,
or vice-versa, or any widening (not just same-size) conversion that
isLosslesslyConvertibleTo approves. This fixes oopack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7288 91177308-0d34-0410-b5e6-96231b3b80d8
Printer::doFinalization() out in the cold. Now we pass in a TargetMachine
to Printer's constructor and get the TargetData from the TargetMachine.
Don't pass TargetMachine or MRegisterInfo objects around in the Printer.
Constify TargetData references.
X86.h: Update comment and prototype of createX86CodePrinterPass().
X86TargetMachine.cpp: Update callers of createX86CodePrinterPass().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7275 91177308-0d34-0410-b5e6-96231b3b80d8
Stop passing ostreams around: we already have one perfectly good ostream
and we can all share it.
Stop stashing a pointer to TargetData in the Pass object, because that will
lead to a crash if there are no functions in the module (ouch!) Instead,
use addRequired() and getAnalysis(), like we always should have done.
Move the check for ConstantExpr up before the check for isPrimitiveType,
because we need to be able to catch e.g. ubyte (cast bool false to ubyte),
whose type is primitive but which is nevertheless a ConstantExpr, by calling
our specialized handler instead of the AsmWriter. This would result in
assembler errors when we would try to output something like ".byte (cast
bool false to ubyte)".
GC some unused variable declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7265 91177308-0d34-0410-b5e6-96231b3b80d8
Avoid a fall-through in the (stubby) treatment of the longjmp intrinsic
call which causes llc & lli to core-dump.
Add a sort-of treatment of cast double to ulong. I am not really sure
what a user should expect to see upon casting a negative FP value to
unsigned long long. But with what is given here, I was able to write
a program that could cast -123.456 to ulong and back and get -123.0,
which seems like a step in the right direction. GCC seems to give you
0. I don't know if I'd consider that useful.
These cases were coming up in GNU coreutils-5.0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7205 91177308-0d34-0410-b5e6-96231b3b80d8
now works in instructions which require a 2-bit or 3-bit INTcc code.
Incidentally, that means that the representation of INTcc registers is now the
same in both integer and FP instructions. Thus, code became much simpler and
cleaner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7185 91177308-0d34-0410-b5e6-96231b3b80d8
allow, i.e. make a sequence of instructions to enable an indirect call using
jump-and-link and 2 temporary registers (which we save and ultimately restore).
Warning: if the delay slot of a function call is used to do meaningful work and
not just a NOP, this behavior is incorrect. However, the Sparc backend does not
yet utilize the delay slots effectively, so it is not necessary to make an
overly complicated algorithm for something that's not used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7178 91177308-0d34-0410-b5e6-96231b3b80d8
* FP double registers are now coded correctly
* Removed function which converted registers based on register types, it was
broken (because regTypes are broken)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7175 91177308-0d34-0410-b5e6-96231b3b80d8
out the entire llvm disassembly for the function at global constant-output
time, which caused the assembler to barf in 164.gzip. This fixes that
particular problem (though 164.gzip has other problems with X86 llc.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7168 91177308-0d34-0410-b5e6-96231b3b80d8
Fhourstones, McCat-vor, and many others...)
Printer.cpp: Print implicit uses for AddRegFrm instructions. Break gas
bug workarounds up into separate stanzas of code for each bug. Add new
workarounds for fild and fistp.
X86InstrInfo.def: Add O_ST0 implicit uses for more FP instrs where they
obviously apply. Also add PrintImplUses flags for FP instrs where they
are necessary for gas to understand the output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7165 91177308-0d34-0410-b5e6-96231b3b80d8
(1) Cannot use ANDN(ot), ORN, and XORN for boolean ops, only bitwise ops.
(2) Conditional move instructions must distinguish signed and unsigned
condition codes, e.g., MOVLE vs. MOVLEU.
(3) Conditional-move-on-register was using the cond-move-on-cc opcodes,
which produces a valid-looking instruction with bogus registers!
(4) Here's a really cute one: dividing-by-2^k for negative numbers needs to
add 2^k-1 before shifting, not add 1 after shifting. Sadly, these
are the same when k=0 so our poor test case worked fine.
(5) Casting between signed and unsigned values was not correct:
completely reimplemented.
(6) Zero-extension on unsigned values was bogus: I was only doing the
SRL and not the SLLX before it. Don't know WHAT I was thinking!
(7) And the most important class of changes: Sign-extensions on signed values.
Signed values are not sign-extended after ordinary operations,
so they must be sign-extended before the following cases:
-- passing to an external or unknown function
-- returning from a function
-- using as operand 2 of DIV or REM
-- using as either operand of condition-code setting operation
(currently only SUBCC), with smaller than 32-bit operands
Also, a couple of improvements:
(1) Fold cast-to-bool into Not(bool). Need to do this for And, Or, XOR also.
(2) Convert SetCC-Const into a conditional-move-on-register (case 41)
if the constant is 0. This was only being done for branch-on-SetCC-Const
when the branch is folded with the SetCC-Const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7159 91177308-0d34-0410-b5e6-96231b3b80d8
(1) An int CC live range must be spilled if there are any interferences,
even if no other "neighbour" in the interf. graph has been allocated
that reg. yet. This is actually true of any class with only one reg!
(2) SparcIntCCRegClass::colorIGNode sets the color even if the LR must
be spilled so that the machine-independent spill code doesn't have to
make the machine-dependent decision of which CC name to use based on
operand type: %xcc or %icc. (These are two halves of the same
register.)
(3) LR->isMarkedForSpill() is no longer the same as LR->hasColor().
These should never have been the same, and this is necessary now for #2.
(4) All RDCCR and WRCCR instructions are directly generated with the
phony number for %ccr so that EmitAssembly/EmitBinary doesn't have to
deal with this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7152 91177308-0d34-0410-b5e6-96231b3b80d8
(1) An int CC live range must be spilled if there are any interferences,
even if no other "neighbour" in the interf. graph has been allocated
that reg. yet. This is actually true of any class with only one reg!
(2) SparcIntCCRegClass::colorIGNode sets the color even if the LR must
be spilled so that the machine-independent spill code doesn't have to
make the machine-dependent decision of which CC name to use based on
operand type: %xcc or %icc. (These are two halves of the same register.)
(3) LR->isMarkedForSpill() is no longer the same as LR->hasColor().
These should never have been the same, and this is necessary now for #2.
(4) All RDCCR and WRCCR instructions are directly generated with the
phony number for %ccr so that EmitAssembly/EmitBinary doesn't have to
deal with this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7151 91177308-0d34-0410-b5e6-96231b3b80d8
