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5 Commits

Author SHA1 Message Date
Vincent Lejeune
bb25a01d23 R600: Non vector only instruction can be scheduled on trans unit 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189980 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-04 19:53:46 +00:00
Tom Stellard
6b3f6a744a Revert "R600: Non vector only instruction can be scheduled on trans unit" 
This reverts commit 98ce62780e.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187526 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-31 20:43:27 +00:00
Vincent Lejeune
98ce62780e R600: Non vector only instruction can be scheduled on trans unit 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187514 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-31 19:31:56 +00:00
Tom Stellard
1f67c63cb2 DAGCombiner: Pass the correct type to TargetLowering::isF(Abs|Neg)Free 
This commit also implements these functions for R600 and removes a test
case that was relying on the buggy behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187007 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-23 23:55:03 +00:00
Tom Stellard
d7a472c9c6 R600: Expand vector FNEG 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186913 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-23 01:47:46 +00:00