Commit Graph

73575 Commits

Author SHA1 Message Date
Dan Bailey
0b19acbb8f PTX: corrected tests that were failing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133875 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25 19:41:17 +00:00
Chad Rosier
14d71aac84 Replace dyn_cast<> with cast<> since the cast is already guarded by the necessary check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133874 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25 18:51:28 +00:00
Dan Bailey
84149460d5 PTX: Reverting implementation of i8.
The .b8 operations in PTX are far more limiting than I first thought. The mov operation isn't even supported, so there's no way of converting a .pred value into a .b8 without going via .b16, which is
not sensible. An improved implementation needs to use the fact that loads and stores automatically extend and truncate to implement support for EXTLOAD and TRUNCSTORE in order to correctly support
boolean values.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133873 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25 18:16:28 +00:00
Michael J. Spencer
25b15777df Object: Add proper error handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133872 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25 17:55:23 +00:00
Michael J. Spencer
76fb9b0e5f Modify llvm-nm to use new Binary creation method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133871 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25 17:54:59 +00:00
Michael J. Spencer
001c9205fc Make Binary the parent of ObjectFile and update children to new interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133870 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25 17:54:50 +00:00
Michael J. Spencer
c44c915372 Add Binary class. This is a cleaner parent than ObjectFile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133869 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25 17:54:29 +00:00
Michael J. Spencer
d2a02f409e Add Object/Error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133868 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25 17:42:56 +00:00
Nick Lewycky
3e64427cb3 Enhance the sanity check for block sizes; check that the resulting pointer is
pointing to the range [first character, last character] instead of just not
after the last character. Patch by Yan Ivnitskiy!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133867 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25 17:08:50 +00:00
Chad Rosier
644eb9befc Test case for r133858 (tail call optimize in the presence of byval).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133863 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25 02:44:56 +00:00
Oscar Fuentes
fdfd40b5f1 Update CMake library dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133859 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25 02:10:19 +00:00
Chad Rosier
df78fcd2d6 Enable tail call optimization in the presence of a byval (x86-32 and x86-64).
<rdar://problem/9483883>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133858 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25 02:04:56 +00:00
Jim Grosbach
75c2b2028b Move ARM-specific test to ARM directory.
Hopefully make the x86-target-only Windows bots happy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133856 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25 01:53:17 +00:00
Douglas Gregor
ba3dc10702 Unbreak CMake build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133853 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25 00:51:50 +00:00
Evan Cheng
025b37b5f0 Remove dead typedefs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133851 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25 00:27:17 +00:00
Evan Cheng
4219718180 Add include guard.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133847 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 23:59:54 +00:00
Evan Cheng
46af0d7341 Rename TargetDesc to MCTargetDesc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133846 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 23:53:19 +00:00
Evan Cheng
5e6b4605bd Rename TargetRegisterDesc to MCRegisterDesc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133845 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 23:44:48 +00:00
Jim Grosbach
ba8297ec08 Refactor MachO relocation generaration into the Target directories.
Move the target-specific RecordRelocation logic out of the generic MC
MachObjectWriter and into the target-specific object writers. This allows
nuking quite a bit of target knowledge from the supposedly target-independent
bits in lib/MC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133844 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 23:44:37 +00:00
Owen Anderson
e6b8bf8c4a The scheduler needs to be aware on the existence of untyped nodes when it performs type propagation for EXTRACT_SUBREG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133838 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 23:02:22 +00:00
Bob Wilson
9c99cfef93 Revert "Shorten some ARM builtin names by removing unnecessary "neon" prefix."
Sorry, this was a bad idea.  Within clang these builtins are in a separate
"ARM" namespace, but the actual builtin names should clearly distinguish that
they are target specific.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133832 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 22:13:17 +00:00
Rafael Espindola
1189027f9d Fix cmake build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133830 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 22:01:28 +00:00
Devang Patel
fa3f9c001f Fix struct member's scope. Patch by Xi Wang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133828 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 22:00:39 +00:00
Bob Wilson
e9e0e3aeaf Shorten some ARM builtin names by removing unnecessary "neon" prefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133825 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 21:32:40 +00:00
Chad Rosier
2416da36ac Hoist simple check above more complex checking to avoid unnecessary
overheads.  No functional change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133824 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 21:15:36 +00:00
Jim Grosbach
56fc642000 Testcase for r133818
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133823 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 20:59:01 +00:00
Devang Patel
0f03782d16 Revert unintentional check-in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133822 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 20:48:14 +00:00
Devang Patel
8594d429e0 Handle debug info for i128 constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133821 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 20:46:11 +00:00
Evan Cheng
f5fa52ed06 - Add MCRegisterInfo registration machinery. Also added x86 registration routines.
- Rename TargetRegisterDesc to MCRegisterDesc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133820 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 20:42:09 +00:00
Jim Grosbach
8b45456700 ARM movw/movt fixups need to mask the high bits.
The fixup value comes in as the whole 32-bit value, so for the lo16 fixup,
the upper bits need to be masked off. Previously we assumed the masking had
already been done and asserted.

rdar://9635991

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133818 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 20:06:59 +00:00
Jim Grosbach
32e7abd080 tidy up whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133815 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 19:43:27 +00:00
Dan Bailey
b05a8a8f02 PTX: Add support for i8 type and introduce associated .b8 registers
The i8 type is required for boolean values, but can only use ld, st and mov instructions. The i1 type continues to be used for predicates.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133814 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 19:27:10 +00:00
Chad Rosier
ef01edf1e9 The Neon VCVT (between floating-point and fixed-point, Advanced SIMD)
instructions can be used to match combinations of multiply/divide and VCVT 
(between floating-point and integer, Advanced SIMD).  Basically the VCVT 
immediate operand that specifies the number of fraction bits corresponds to a 
floating-point multiply or divide by the corresponding power of 2.

For example, VCVT (floating-point to fixed-point, Advanced SIMD) can replace a 
combination of VMUL and VCVT (floating-point to integer) as follows:

Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
  vmul.f32        d16, d17, d16
  vcvt.s32.f32    d16, d16
becomes:
  vcvt.s32.f32    d16, d16, #3

Similarly, VCVT (fixed-point to floating-point, Advanced SIMD) can replace a 
combinations of VCVT (integer to floating-point) and VDIV as follows:

Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
  vcvt.f32.s32    d16, d16
  vdiv.f32        d16, d17, d16
becomes:
  vcvt.f32.s32    d16, d16, #3

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133813 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 19:23:04 +00:00
Justin Holewinski
4799729d67 PTX: Add preliminary support for outputting debug information in the form of
.file and .loc directives.

Ideally, we would utilize the existing support in AsmPrinter for this, but
I cannot find a way to get .file and .loc directives to print without the
rest of the associated DWARF sections, which ptxas cannot handle.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133812 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 19:19:18 +00:00
Akira Hatanaka
25eba399cb Change the chain input of nodes that load the address of a function. This change
enables SelectionDAG::getLoad at MipsISelLowering.cpp:1914 to return a
pre-existing node instead of redundantly create a new node every time it is
called.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133811 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 19:01:25 +00:00
Jim Grosbach
535e58b910 Fixup info for Thumb2 unconditional branch.
rdar://9667872

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133808 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 18:48:32 +00:00
Akira Hatanaka
8b2b713f68 Prevent generation of redundant addiu instructions that compute address of
static variables or functions. 




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133803 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 17:55:19 +00:00
Justin Holewinski
35f4fb34ff PTX: Re-work target sm/compute selection and add some basic GPU
targets: g80, gt200, gf100(fermi)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133799 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 16:27:49 +00:00
Rafael Espindola
40179bf874 Simplify
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133798 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 15:50:56 +00:00
Rafael Espindola
d7f35fa824 Now that bb with phis are not considered simple, duplicate them even if
we cannot duplicate to every predecessor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133797 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 15:47:41 +00:00
Rafael Espindola
1f71549a2e Simplify now that blocks with phis are not considered simple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133793 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 14:04:13 +00:00
Rafael Espindola
ce117be633 Fix CellSPU CMakeList.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133792 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 13:58:45 +00:00
Benjamin Kramer
5c10b63969 Make the generated InitXXXMCRegisterInfo function "static inline", so it doesn't get emitted into multiple object files.
This caused linker errors when linking both libLLVMX86Desc and libLLVMX86CodeGen
into a single binary (for example when building a monolithic libLLVM shared library).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133791 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 11:03:31 +00:00
Evan Cheng
6db5d55ec3 Fix CellSPU CMakeLists.txt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133787 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 05:04:48 +00:00
Evan Cheng
a347f85dbe Starting to refactor Target to separate out code that's needed to fully describe
target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.

First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 01:44:41 +00:00
Jakub Staszak
66dddd1da3 Calculate backedge probability correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133776 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-23 23:52:11 +00:00
Jim Grosbach
0edb05b9e4 Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133770 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-23 22:29:00 +00:00
Jakub Staszak
fd9533b4a3 Missing files for the BlockFrequency analysis added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133767 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-23 21:56:59 +00:00
Jakub Staszak
44eb49c2a1 Introduce BlockFrequency analysis for BasicBlocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133766 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-23 21:45:20 +00:00
Eli Friedman
a390a1aa48 Add support for movntil/movntiq mnemonics. Reported on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133759 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-23 21:07:47 +00:00