d89ae99ec8
X86FastISel support for conditional branches.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55816 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-05 01:06:14 +00:00
95267a1e67
Add initial support for selecting constant materializations that require constant
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pool loads on X86 in fast isel. This isn't actually used yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55814 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-05 00:06:23 +00:00
6e3f05f5ce
X86FastISel support for ICmpInst and FCmpInst.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55811 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-04 23:26:51 +00:00
79924eb6f5
Fix the ordering of operands to the store (inverted relative to LLVM IR), and fix the testcase.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55777 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-04 16:48:33 +00:00
a3971dfbfe
Add a first attempt at implementing stores for X86 fast isel using target hooks.
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Dan or Evan, please review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55764 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-04 07:08:58 +00:00
373d50af1d
Load from GV stub should be locally CSE'd.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55763 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-04 06:18:33 +00:00
3df24e667f
Create HandlePHINodesInSuccessorBlocksFast, a version of
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HandlePHINodesInSuccessorBlocks that works FastISel-style. This
allows PHI nodes to be updated correctly while using FastISel.
This also involves some code reorganization; ValueMap and
MBBMap are now members of the FastISel class, so they needn't
be passed around explicitly anymore. Also, SelectInstructions
is changed to SelectInstruction, and only does one instruction
at a time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55746 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-03 23:12:08 +00:00
8b19e56051
Add X86 target hook to implement load (even from GlobalAddress).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55693 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-03 06:44:39 +00:00
88e3041ca6
Unbreak fast isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55685 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-03 01:04:47 +00:00
c3f44b0d63
Let tblgen only generate fastisel routines, not the class definition. This makes it easier for targets to define its own fastisel class.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55679 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-03 00:03:49 +00:00
667d8f7607
Add initial support for fast isel of instructions that have inputs pinned to physical registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55545 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29 17:45:56 +00:00
99b218218c
Add a target callback for FastISel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55512 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28 23:21:34 +00:00
22bb31103d
Factor out the predicate check code from DAGISelEmitter.cpp
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and use it in FastISelEmitter.cpp, and make FastISel
subtarget aware. Among other things, this lets it work
properly on x86 targets that don't have SSE, where it
successfully selects x87 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55156 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-22 00:20:26 +00:00
1adf1b03af
Instantiate FastISel for X86.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55011 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-19 21:45:35 +00:00
