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368e18d56a
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382 Commits

Author SHA1 Message Date
Nate Begeman
368e18d56a Rework the SelectionDAG-based implementations of SimplifyDemandedBits 
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26238 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-16 21:11:51 +00:00
Evan Cheng
a03a5dc7ce Rename maxStoresPerMemSet to maxStoresPerMemset, etc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26174 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-14 08:38:30 +00:00
Chris Lattner
eac707f702 getConstraintType should be virtual. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26041 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-07 20:13:44 +00:00
Chris Lattner
c991cf58aa Add some methods for inline asm support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25950 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-04 02:12:09 +00:00
Nate Begeman
de99629e2a Add a framework for eliminating instructions that produces undemanded bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25945 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-03 22:24:05 +00:00
Chris Lattner
af9fa2bd0c Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo, 
a far more logical place.  Other methods should also be moved if anyone
is interested. :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25912 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-02 20:11:55 +00:00
Chris Lattner
679836360a add a new isStoreToStackSlot method 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25909 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-02 19:55:29 +00:00
Chris Lattner
cb0b555663 Clear the OpAction field before setting it. This allows a target to set 
an instruction operation action to Expand, then set it to Legal later.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25812 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-30 06:09:03 +00:00
Chris Lattner
553d8007ad Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface, 
making isMaskedValueZeroForTargetNode simpler, and useable from other parts
of the compiler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25802 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-30 04:08:18 +00:00
Chris Lattner
030dae5bce Pass the address of the main MaskedValueIsZero function to allow recursion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25797 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-30 03:48:36 +00:00
Chris Lattner
e3bd778e4d Clean up the interface to ValueTypeActions, allowing Legalize to use a copy 
of it more cleanly.  Double the size of OpActions, allowing it to hold actions
for any VT.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25782 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-29 08:40:37 +00:00
Chris Lattner
7e871b28a2 remove this method I just added, now is not the time. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25729 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-28 03:43:33 +00:00
Chris Lattner
4f16e70faa add a new callback 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25727 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-28 03:37:03 +00:00
Nate Begeman
0aed7840ec Implement Promote for VAARG, and allow it to be custom promoted for people 
who don't want the default behavior (Alpha).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25726 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-28 03:14:31 +00:00
Nate Begeman
ee625573b5 Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for 
the same functionality.  This addresses another piece of bug 680.  Next,
on to fixing Alpha VAARG, which I broke last time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25696 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-27 21:09:22 +00:00
Chris Lattner
4ed88eb822 Add a common INLINEASM opcode 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25667 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-26 23:27:02 +00:00
Jeff Cohen
9471c8a93b Improve compatibility with VC2005, patch by Morten Ofstad! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25661 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-26 20:41:32 +00:00
Chris Lattner
bc9ae377d9 Add a method for inline asm support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25656 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-26 20:27:33 +00:00
Nate Begeman
acc398c195 First part of bug 680: 
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25606 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-25 18:21:52 +00:00
Evan Cheng
d854b62afa Add a enum to specify target scheduling preference: SchedulingForLatency or 
SchedulingForRegPressure. Added corresponding methods to set / get the value.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25598 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-25 09:09:02 +00:00
Chris Lattner
2790383f73 Add a new InvalidateStructLayoutInfo method and some comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25303 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-14 00:06:42 +00:00
Chris Lattner
d90ef9ef2b Provide an interface for Targets to specify their stack pointer register 
for llvm.stacksave/restore.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25275 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-13 17:47:52 +00:00
Jeff Cohen
9337de8651 Oh oh... Unix is case sensitive. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24928 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-22 01:46:59 +00:00
Jeff Cohen
f31a60cd71 Make it compile with VC++. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24927 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-22 01:44:51 +00:00
Evan Cheng
c85b33f264 Added TargetLowering::isMaskedValueZeroForTargetNode() declaration. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24923 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-21 23:15:41 +00:00
Evan Cheng
7226158d7e Added a hook to print out names of target specific DAG nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24877 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-20 06:22:03 +00:00
Nate Begeman
6510b22cec Support multiple ValueTypes per RegisterClass, needed for upcoming vector 
work.  This change has no effect on generated code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24563 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-01 04:51:06 +00:00
Nate Begeman
6a648614e8 Add the majority of the vector machien value types we expect to support, 
and make a few changes to the legalization machinery to support more than
16 types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24511 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-29 05:45:29 +00:00
Nate Begeman
395cba8d41 Teach the type lowering code about turning packed types into vector types. 
Next step: generating vector dag nodes, and legalizing them into scalar
code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24404 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-17 21:44:42 +00:00
Chris Lattner
df2e425f2a Add a new option to indicate we want the code generator to emit code quickly, 
not spending tons of time microoptimizing it.  This is useful for an -O0
style of build.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24235 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-08 02:12:47 +00:00
Jeff Cohen
be07f72ca2 <cassert> no longer required to make VC++ happy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24177 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-04 02:59:16 +00:00
Duraid Madina
0954038705 change NULL to 0, unbreaks the ppc target when building on ia64 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24176 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-04 01:45:04 +00:00
Jim Laskey
7f39c14f52 1. Remove ranges from itinerary data. 
2. Tidy up the subtarget emittined code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24172 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-03 22:47:41 +00:00
Jeff Cohen
55d1728ec8 Keep VC++ happy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24148 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-02 04:03:16 +00:00
Jim Laskey
6cee630070 Allow itineraries to be passed through the Target Machine. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24139 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-01 20:06:59 +00:00
Jim Laskey
15517be4bf Structures used to hold scheduling information. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24049 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-27 18:18:05 +00:00
Jim Laskey
34bd5d5d87 Preparation of supporting scheduling info. Need to find info based on selected 
CPU.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23974 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-25 15:15:28 +00:00
Chris Lattner
3e8d596ded Move static functions to .cpp file, reduce #includes, pass strings by 
const&.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23890 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-23 05:25:19 +00:00
Nate Begeman
405e3ecb56 Invert the TargetLowering flag that controls divide by consant expansion. 
Add a new flag to TargetLowering indicating if the target has really cheap
  signed division by powers of two, make ppc use it.  This will probably go
  away in the future.
Implement some more ISD::SDIV folds in the dag combiner
Remove now dead code in the x86 backend.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23853 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-21 00:02:42 +00:00
Nate Begeman
d32d4a93f6 Enable targets to say that integer divide is expensive, which will trigger 
an upcoming optimization in the DAG Combiner.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23834 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-20 02:14:14 +00:00
Nate Begeman
4a95945fa5 Add the ability to lower return instructions to TargetLowering. This 
allows us to lower legal return types to something else, to meet ABI
requirements (such as that i64 be returned in two i32 regs on Darwin/ppc).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23802 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-18 23:23:37 +00:00
Chris Lattner
a385bf7b6d Fix case of path 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23605 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-03 03:32:39 +00:00
Chris Lattner
9390368970 This member can be const too 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23600 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-03 00:21:25 +00:00
Chris Lattner
4c225baa3e Expose the actual valuetype of each register class 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23583 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-02 06:23:19 +00:00
Chris Lattner
0f21fd5204 Rename MRegisterDesc -> TargetRegisterDesc for consistency 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23564 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 17:49:27 +00:00
Chris Lattner
2f02ed9a1f trim down the target info structs now that we have a preferred spill register class for each callee save register 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23560 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 17:35:22 +00:00
Chris Lattner
2f9dbe8ee6 expose a new virtual method 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23555 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 07:06:37 +00:00
Chris Lattner
294f41d5fc Change these methods to take RC's 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23535 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 01:28:14 +00:00
Chris Lattner
5e93fbe68c Add a new flag for targets where setjmp/longjmp saves/restores the signal mask, 
and _setjmp/_longjmp should be used instead (for llvm.setjmp/llvm.longjmp).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23479 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-27 22:13:36 +00:00
Chris Lattner
7d3041e060 add a new callback 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23373 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-17 01:02:45 +00:00