Commit Graph

91987 Commits

Author SHA1 Message Date
Bill Wendling
3d3a37ed4d Merging r182385:
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r182385 | hfinkel | 2013-05-21 07:21:09 -0700 (Tue, 21 May 2013) | 9 lines

Fix PPC branch selection for counter-based branches

Although I had added some support for the BDZ/BDNZ branches into the selector
(in r158204), I had not correctly adjusted the condition at the top of the
loop. As a result, these branches were still essentially unsupported.

This fixes PR16086. Unfortunately, any test case would be very large (because
it would need to force the loop backedge to exceed the range of the 16-bit
immediate).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182431 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-21 22:11:11 +00:00
Bill Wendling
629c73232c Merging r182387:
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r182387 | jholewinski | 2013-05-21 07:37:16 -0700 (Tue, 21 May 2013) | 7 lines

Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen.

The intrinsic calls are dropped, but the annotated value is propagated.

Fixes PR 15253

Original patch by Zeng Bin!
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2013-05-21 20:23:13 +00:00
Bill Wendling
bb120a12ce Merging r182112:
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r182112 | tstellar | 2013-05-17 08:23:12 -0700 (Fri, 17 May 2013) | 1 line

R600: Pass MCSubtargetInfo reference to R600CodeEmitter
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182416 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-21 20:21:23 +00:00
Bill Wendling
5f5295224d Merging r182364:
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r182364 | d0k | 2013-05-21 02:58:54 -0700 (Tue, 21 May 2013) | 4 lines

X86: When emulating unsigned PCMPGTQ with PCMPGTD, fix the sign bit for the smaller type.

Otherwise we'll get a mix of signed and unsigned compares.
Fixes PR15977.
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2013-05-21 20:13:22 +00:00
Bill Wendling
717979bbd0 Merging r182344:
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r182344 | mren | 2013-05-20 17:57:22 -0700 (Mon, 20 May 2013) | 7 lines

Dwarf: use a single line table to generate assembly when .loc is used.

This is to fix PR15408 where an undefined symbol Lline_table_start1 is used.
Since we do not generate the debug_line section when .loc is used,
Lline_table_start1 is not emitted and we can't refer to it when calculating
at_stmt_list for a compile unit.

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2013-05-21 01:03:46 +00:00
Bill Wendling
a0ff134cc1 Remove 'svn' from version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182312 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 20:18:23 +00:00
Bill Wendling
ca0c1cebe2 Remove the 'svn' from the version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182311 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 20:16:54 +00:00
Bill Wendling
f86bbdcdad Merging r182113:
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r182113 | tstellar | 2013-05-17 08:23:21 -0700 (Fri, 17 May 2013) | 9 lines

R600: Fix encoding for R600 family GPUs

Reviewed-by: Vincent Lejeune <vljn@ovi.com>

https://bugs.freedesktop.org/show_bug.cgi?id=64193
https://bugs.freedesktop.org/show_bug.cgi?id=64257
https://bugs.freedesktop.org/show_bug.cgi?id=64320

NOTE: This is a candidate for the 3.3 branch.
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2013-05-17 23:36:26 +00:00
Bill Wendling
125b4fde3b Merging r181864:
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r181864 | chapuni | 2013-05-14 19:16:23 -0700 (Tue, 14 May 2013) | 10 lines

ELFRelocationEntry::operator<(): Try to stabilize the order. r_offset was insufficient to sort Relocs.

It should fix llvm/test/CodeGen/ARM/ehabi-mc-compact-pr*.ll on some hosts.

  RELOCATION RECORDS FOR [.ARM.exidx]:
  0 R_ARM_PREL31 .text
  0 R_ARM_NONE __aeabi_unwind_cpp_pr0

FIXME: I am not sure of the directions of extra comparators, in Type and Index.
For now, they are different from the direction in r_offset.
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2013-05-17 18:51:33 +00:00
Bill Wendling
ed3c685148 Merging r181706:
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r181706 | rafael | 2013-05-13 07:34:48 -0700 (Mon, 13 May 2013) | 1 line

Remove unused fields and arguments.
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2013-05-17 18:49:56 +00:00
Bill Wendling
1ce52f1601 Merging r181678:
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r181678 | rafael | 2013-05-12 17:18:24 -0700 (Sun, 12 May 2013) | 1 line

XFAIL this test for mingw too.
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2013-05-17 18:49:16 +00:00
Bill Wendling
e07b0900bf Merging r181600:
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r181600 | aaronballman | 2013-05-10 07:42:16 -0700 (Fri, 10 May 2013) | 1 line

XFAILing this test on Win32 to unbreak the build bots.
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2013-05-17 18:48:58 +00:00
Bill Wendling
b986017e2e Merging r182072:
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2013-05-17 18:46:38 +00:00
Bill Wendling
5b39b74a3f Merging r181529:
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r181529 | void | 2013-05-09 11:21:45 -0700 (Thu, 09 May 2013) | 8 lines

Simplify the code a bit.

The compact unwind registers were defined in two different
places. It's better just to place them in the function that uses them
and specify that this is a 64-bit or 32-bit machine.

No functionality change.

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2013-05-16 00:30:10 +00:00
Bill Wendling
2fc0483faf Merging r181540:
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r181540 | void | 2013-05-09 13:10:38 -0700 (Thu, 09 May 2013) | 11 lines

Generate a compact unwind encoding in the face of a stack alignment push.

We generate a `push' of a random register (%rax) if the stack needs to be
aligned by the size of that register. However, this could mess up compact unwind
generation. In particular, we want to still generate compact unwind in the
presence of this monstrosity.

Check if the push of of the %rax/%eax register. If it is and it's marked with
the `FrameSetup' flag, then we can generate a compact unwind encoding for the
function only if the push is the last FrameSetup instruction.

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2013-05-16 00:29:29 +00:00
Bill Wendling
d9b720d279 Merging r181580:
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r181580 | tstellar | 2013-05-09 19:09:45 -0700 (Thu, 09 May 2013) | 10 lines

R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen patterns

The BFE optimization was the only one we were actually using, and it was
emitting an intrinsic that we don't support.

https://bugs.freedesktop.org/show_bug.cgi?id=64201

Reviewed-by: Christian König <christian.koenig@amd.com>

NOTE: This is a candidate for the 3.3 branch.
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2013-05-16 00:27:57 +00:00
Bill Wendling
91310e4a30 Merging r181579:
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r181579 | tstellar | 2013-05-09 19:09:39 -0700 (Thu, 09 May 2013) | 8 lines

R600: Expand SUB for v2i32/v4i32

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>

NOTE: This is a candidate for the 3.3 branch.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181953 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16 00:27:42 +00:00
Bill Wendling
3e17699c38 Merging r181578:
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r181578 | tstellar | 2013-05-09 19:09:34 -0700 (Thu, 09 May 2013) | 10 lines

R600: Expand MUL for v4i32/v2i32

Fixes piglit test for OpenCL builtin mul24, and allows mad24 to run.

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>

NOTE: This is a candidate for the 3.3 branch.
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2013-05-16 00:27:29 +00:00
Bill Wendling
0b74e32c2e Merging r181577:
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r181577 | tstellar | 2013-05-09 19:09:29 -0700 (Thu, 09 May 2013) | 10 lines

R600: Expand SRA for v4i32/v2i32

v2: Add v4i32 test

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>

NOTE: This is a candidate for the 3.3 branch.
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2013-05-16 00:27:17 +00:00
Bill Wendling
717969d98f Merging r181576:
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r181576 | tstellar | 2013-05-09 19:09:24 -0700 (Thu, 09 May 2013) | 10 lines

R600: Expand vselect for v4i32 and v2i32

v2: Add vselect v4i32 test

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>

NOTE: This is a candidate for the 3.3 branch.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181950 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16 00:27:04 +00:00
Bill Wendling
89b909942f Merging r181792:
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r181792 | tstellar | 2013-05-14 07:42:56 -0700 (Tue, 14 May 2013) | 8 lines

R600/SI: Add processor type for Hainan asic

Patch by: Alex Deucher

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

NOTE: This is a candidate for the 3.3 branch.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181949 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16 00:16:45 +00:00
Bill Wendling
a3d7a30740 Merging r181842:
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r181842 | arnolds | 2013-05-14 15:33:24 -0700 (Tue, 14 May 2013) | 14 lines

ARM ISel: Don't create illegal types during LowerMUL

The transformation happening here is that we want to turn a
"mul(ext(X), ext(X))" into a "vmull(X, X)", stripping off the extension. We have
to make sure that X still has a valid vector type - possibly recreate an
extension to a smaller type. In case of a extload of a memory type smaller than
64 bit we used create a ext(load()). The problem with doing this - instead of
recreating an extload - is that an illegal type is exposed.

This patch fixes this by creating extloads instead of ext(load()) sequences.

Fixes PR15970.

radar://13871383
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181946 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-15 23:41:52 +00:00
Bill Wendling
5b85a9b5ad Merging r181524:
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r181524 | rafael | 2013-05-09 10:22:59 -0700 (Thu, 09 May 2013) | 4 lines

Don't replace an alias in llvm.used with its target.

When we replace an internal alias with its target, be careful not to
replace the entry in llvm.used (and llvm.compiler_used).
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2013-05-15 18:16:42 +00:00
Bill Wendling
b1ecefd0b5 Merging r181450:
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r181450 | uweigand | 2013-05-08 10:50:07 -0700 (Wed, 08 May 2013) | 16 lines


[PowerPC] Fix regression in generating @ha/@l relocs

The patch I committed as revision 167864 introduced a regression that
causes LLVM to no longer generate appropriate relocs for @ha/@l symbol
references (but fail an assertion instead).

This is fixed here by re-enabling support for the VK_PPC_GAS_HA16/
VK_PPC_GAS_LO16 variant kinds (and their Darwin variants) in
PPCELFObjectWriter.cpp.

Tested by running projects/test-suite in -m32 mode with the integrated
assembler forced on.  A standalone test case will be committed shortly
as well.


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2013-05-14 18:35:11 +00:00
Bill Wendling
52b488a3f8 Merging r181800:
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r181800 | wschmidt | 2013-05-14 09:08:32 -0700 (Tue, 14 May 2013) | 15 lines

PPC32: Fix stack collision between FP and CR save areas.

The changes to CR spill handling missed a case for 32-bit PowerPC.
The code in PPCFrameLowering::processFunctionBeforeFrameFinalized()
checks whether CR spill has occurred using a flag in the function
info.  This flag is only set by storeRegToStackSlot and
loadRegFromStackSlot.  spillCalleeSavedRegisters does not call
storeRegToStackSlot, but instead produces MI directly.  Thus we don't
see the CR is spilled when assigning frame offsets, and the CR spill
ends up colliding with some other location (generally the FP slot).

This patch sets the flag in spillCalleeSavedRegisters for PPC32 so
that the CR spill is properly detected and gets its own slot in the
stack frame.

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2013-05-14 18:34:27 +00:00
Bill Wendling
06362e2450 Merging r181586:
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r181586 | d0k | 2013-05-10 02:16:52 -0700 (Fri, 10 May 2013) | 3 lines

InstCombine: Verify the type before transforming uitofp into select.

PR15952.
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2013-05-14 18:30:01 +00:00
Andrew Kaylor
30b015f044 Fixing MCJIT unit test on Windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181625 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 20:28:44 +00:00
Bill Wendling
0a3c6b4fcc Merging r181397:
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r181397 | nicholas | 2013-05-08 02:00:10 -0700 (Wed, 08 May 2013) | 3 lines

Fix a bug in codegenprep where it was losing track of values OptimizeMemoryInst
by switching to a ValueMap. Patch by Andrea DiBiagio!

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181619 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 18:23:11 +00:00
Bill Wendling
5f32469bd4 Merging r181423:
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r181423 | hfinkel | 2013-05-08 05:16:14 -0700 (Wed, 08 May 2013) | 5 lines

PPCInstrInfo::optimizeCompareInstr should not optimize FP compares

The floating-point record forms on PPC don't set the condition register bits
based on a comparison with zero (like the integer record forms do), but rather
based on the exception status bits.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181507 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-09 07:33:50 +00:00
Bill Wendling
c7594e48ed Merging r181286:
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r181286 | arnolds | 2013-05-06 21:37:05 -0700 (Mon, 06 May 2013) | 7 lines

LoopVectorize: getConsecutiveVector must respect signed arithmetic

We were passing an i32 to ConstantInt::get where an i64 was needed and we must
also pass the sign if we pass negatives numbers. The start index passed to
getConsecutiveVector must also be signed.

Should fix PR15882.
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2013-05-08 18:13:06 +00:00
Richard Sandiford
8f2d9a793d Merge of r181434
Add myself as SystemZ code owner


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181435 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-08 14:42:12 +00:00
Richard Sandiford
aae91f7df0 Merge of r181431
Add SystemZ feats to CodeGenerator.rst


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181432 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-08 14:26:00 +00:00
Richard Sandiford
56f463ab31 Merge of r181328
Mention SystemZ in the release notes


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181427 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-08 13:51:45 +00:00
Richard Sandiford
93618a91c6 Merge of r181312
[SystemZ] Fix InitMCCodeGenInfo call

createSystemZMCCodeGenInfo was not passing the optimization level to
InitMCCodeGenInfo(), so -O0 would be ignored.  Fixes DebugInfo/namespace.ll
after the changes in r181271.


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2013-05-08 09:40:09 +00:00
Bill Wendling
b3f0d9ddac Update to ToT's version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181403 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-08 09:24:11 +00:00
Bill Wendling
da04487b82 Merging r181313:
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r181313 | mkuper | 2013-05-07 07:05:33 -0700 (Tue, 07 May 2013) | 1 line

Re-enable AVX detection on x64 platforms.
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2013-05-08 09:15:09 +00:00
Bill Wendling
5706fb9af2 Turn off binary comparison for 3.3 release.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181398 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-08 09:12:32 +00:00
Bill Wendling
f4e04ae3a7 Merging r181296:
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r181296 | timurrrr | 2013-05-07 00:47:47 -0700 (Tue, 07 May 2013) | 1 line

Fix the VS2010 build broken by r181271
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2013-05-08 00:28:30 +00:00
Bill Wendling
9fc5105a7c Creating release_33 branch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181273 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 00:13:38 +00:00
David Blaikie
d2e0f7ee15 DebugInfo: Support imported modules in lexical blocks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181271 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 23:33:07 +00:00
Tom Stellard
3d834a44f6 R600/SI: Add intrinsic for MIMG IMAGE_GET_RESINFO opcode
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

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2013-05-06 23:02:19 +00:00
Tom Stellard
ea73bd8a54 R600/SI: Handle arbitrary destination type in SITargetLowering::adjustWritemask
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

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2013-05-06 23:02:15 +00:00
Tom Stellard
651a4c8ee0 R600/SI: Add intrinsic for texture image loading
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

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2013-05-06 23:02:12 +00:00
Tom Stellard
e756ffd888 R600/SI: Add pattern for uint_to_fp
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

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2013-05-06 23:02:07 +00:00
Tom Stellard
586862ae23 R600/SI: Add patterns for integer maxima / minima
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

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2013-05-06 23:02:04 +00:00
Tom Stellard
354769ba32 R600/SI: Add pattern for AMDGPU.trunc intrinsic
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

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2013-05-06 23:02:00 +00:00
Krzysztof Parzyszek
942940a326 Print IR from Hexagon MI passes with -print-before/after-all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181255 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 21:58:00 +00:00
Andrew Trick
61e0172197 Implemented public interface for modifying registered (not positional or sink options) command line options at runtime.
Patch by Dan Liew!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181254 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 21:56:35 +00:00
Andrew Trick
b7ad33b719 Support command line option categories.
Patch by Dan Liew!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181253 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 21:56:23 +00:00
Krzysztof Parzyszek
b072090f39 Cleanup of the HexagonTargetMachine setup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181250 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 21:25:45 +00:00