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1230 Commits

Author SHA1 Message Date
Eli Friedman
3dad610aaa Make GlobalMerge honor the preferred alignment on globals without an explicitly specified alignment. 
<rdar://problem/10497732>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145523 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 21:54:15 +00:00
Jakob Stoklund Olesen
7c6b2c9a70 FileCheckize. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145452 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 23:09:16 +00:00
Chad Rosier
ae6f2cb1fc If fast-isel fails, remove dead instructions generated during the failed 
attempt.  

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145425 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 19:40:47 +00:00
Evan Cheng
1c487869f5 DAG combine should not increase alignment of loads / stores with alignment less 
than ABI alignment. These are loads / stores from / to "packed" data structures.
Their alignments are intentionally under-specified.

rdar://10301431


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145273 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-28 20:42:56 +00:00
Chris Lattner
d2bf432b2b Upgrade syntax of tests using volatile instructions to use 'load volatile' instead of 'volatile load', which is archaic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145171 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-27 06:54:59 +00:00
Chad Rosier
478b06c980 When fast iseling a GEP, accumulate the offset rather than emitting a series of 
ADDs.  MaxOffs is used as a threshold to limit the size of the offset. Tradeoffs
being: (1) If we can't materialize the large constant then we'll cause fast-isel
to bail. (2) Too large of an offset can't be directly encoded in the ADD
resulting in a MOV+ADD.  Generally not a bad thing because otherwise we would
have had ADD+ADD, but on Thumb this turns into a MOVS+MOVT+ADD. Working on a fix
for that. (3) Conversely, too low of a threshold we'll miss opportunities to 
coalesce ADDs.
rdar://10412592



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144886 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-17 07:15:58 +00:00
Evan Cheng
eaa192af18 Add vmov.f32 to materialize f32 immediate splats which cannot be handled by 
integer variants. rdar://10437054


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144608 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 02:12:34 +00:00
Jim Grosbach
ffc658b056 ARM VLDR/VSTR instructions don't need a size suffix. 
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:03:21 +00:00
Chad Rosier
e91da1baa1 Add newline to end of file. Thanks, Eli. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144579 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 22:48:33 +00:00
Chad Rosier
909cb4f2f2 Add support for inlining small memcpys. 
rdar://10412592


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144578 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 22:46:17 +00:00
Chad Rosier
e489af8dce Fix a performance regression from r144565. Positive offsets were being lowered 
into registers, rather then encoded directly in the load/store.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144576 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 22:34:48 +00:00
Chad Rosier
57b2997966 Add support for Thumb load/stores with negative offsets. 
rdar://10412592



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144565 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 20:22:27 +00:00
Jakob Stoklund Olesen
f054e19819 Fix early-clobber handling in shrinkToUses. 
I broke this in r144515, it affected most ARM testers.

<rdar://problem/10441389>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144547 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 18:45:38 +00:00
Jakob Stoklund Olesen
4a9b615f3e Delete stale comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144542 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 18:03:05 +00:00
Chad Rosier
dc9205d9c2 Add support for ARM halfword load/stores and signed byte loads with negative 
offsets.
rdar://10412592



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144518 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 04:09:28 +00:00
Chad Rosier
9eb674880b The order in which the predicate is added differs between Thumb and ARM mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144494 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-13 09:44:21 +00:00
Chad Rosier
a517ab155b Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing failures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144492 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-13 05:14:43 +00:00
Chad Rosier
b29b950bf2 Add support for emitting both signed- and zero-extend loads. Fix 
SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8
offsets (addressing mode 3).  This enables a load followed by an integer 
extend to be folded into a single load.

For example:
ldrb r1, [r0]       ldrb r1, [r0]
uxtb r2, r1     =>
mov  r3, r2         mov  r3, r1


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144488 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-13 02:23:59 +00:00
Jakob Stoklund Olesen
5d9b109181 Delete the 'standard' spiller with used the old spilling framework. 
The current register allocators all use the inline spiller.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144477 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-12 23:29:02 +00:00
Jakob Stoklund Olesen
56ad83d47c RAGreedy is better about hinting now. 
Or maybe we are just getting lucky.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144473 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-12 22:39:37 +00:00
Jakob Stoklund Olesen
7f67091259 Linear scan is going away. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144472 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-12 22:39:34 +00:00
Jakob Stoklund Olesen
2eda9458ea XFAIL test that depends on linear scan to remove dead code. 
Filed PR11364 to track the problem.  Should the register allocator
eliminate dead code?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144471 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-12 22:39:30 +00:00
Jakob Stoklund Olesen
097d277ef0 Switch a few tests off linearscan. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144460 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-12 19:53:52 +00:00
Eli Friedman
501852423d Don't try to form pre/post-indexed loads/stores until after LegalizeDAG runs. Fixes PR11029. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144438 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-12 00:35:34 +00:00
Chad Rosier
11add26ec2 Add support in fast-isel for selecting memset/memcpy/memmove intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144426 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 23:31:03 +00:00
Chad Rosier
6d267449ac Loosen test by using REs. Approved by Devang. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144425 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 23:25:38 +00:00
Andrew Trick
95bc85e4ee Preserve MachineMemOperands in ARMLoadStoreOptimizer. 
Fixes PR8113.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144409 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 22:18:09 +00:00
Chad Rosier
a07d3fc693 Add support for using immediates with select instructions. 
rdar://10412592


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144376 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 06:20:39 +00:00
Eli Friedman
15f58c56e9 Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144361 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 03:16:38 +00:00
Chad Rosier
4e89d97e3a Add support for using MVN to materialize negative constants. 
rdar://10412592

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144348 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 00:36:21 +00:00
Chad Rosier
16455ce1a4 When in ARM mode, LDRH/STRH require special handling of negative offsets. 
For correctness, disable this for now.
rdar://10418009

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144316 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 21:09:49 +00:00
Chad Rosier
6cba97c555 For immediate encodings of icmp, zero or sign extend first. Then 
determine if the value is negative and flip the sign accordingly.
rdar://10422026

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144258 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 01:30:39 +00:00
Eli Friedman
14e809c872 Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144241 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 23:36:02 +00:00
Eli Friedman
0948f0acca Add check so we don't try to perform an impossible transformation. Fixes issue from PR11319. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144216 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 22:25:12 +00:00
Chad Rosier
a7a996b98d Use REs to remove dependencies on the register allocation order. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144209 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 20:06:13 +00:00
Chad Rosier
2f2fe417f9 Add support for encoding immediates in icmp and fcmp. Hopefully, this will 
remove a fair number of unnecessary materialized constants.
rdar://10412592


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144163 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 03:22:02 +00:00
Evan Cheng
3568a1051e Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with ldm or ldr pairs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144123 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 21:21:09 +00:00
Lang Hames
5207bf2177 Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported. 
Add support for trimming constants to GetDemandedBits. This fixes some funky
constant generation that occurs when stores are expanded for targets that don't
support unaligned stores natively.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144102 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 18:56:23 +00:00
Eli Friedman
9f1f26aefa Make sure to mark vector extload's as expand on ARM. Fixes PR11319. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144057 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 01:43:53 +00:00
Bill Wendling
30ceba32b2 Convert tests to the new EH model. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144048 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 00:09:27 +00:00
Chad Rosier
0eff39f2e2 Enable support for returning i1, i8, and i16. Nothing special todo as it's the 
callee's responsibility to sign or zero-extend the return value.  The additional
test case just checks to make sure the calls are selected (i.e., -fast-isel-abort
doesn't assert).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144047 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 00:03:32 +00:00
Benjamin Kramer
70be28a5ad Simplify some uses of utohexstr. 
As a side effect hex is printed lowercase instead of uppercase now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144013 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 21:00:59 +00:00
Chad Rosier
42536af5ce Add support for passing i1, i8, and i16 call parameters. Also, be sure to 
zero-extend the constant integer encoding.  Test case provides testing for
both call parameters and materialization of i1, i8, and i16 types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143821 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-05 20:16:15 +00:00
Benjamin Kramer
c25c908977 Add an option to pad an uleb128 to MCObjectWriter and remove the uleb128 encoding from the DWARF asm printer. 
As a side effect we now print dwarf ulebs with .ascii directives.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143809 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-05 11:52:44 +00:00
Chad Rosier
f470cbbad2 Add fast-isel support for returning i1, i8, and i16. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143669 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-04 00:50:21 +00:00
Chad Rosier
463fe24f1d Add support for sign-extending non-legal types in SelectSIToFP(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143603 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-03 02:04:59 +00:00
Lang Hames
1a1d1fcc0b Try to lower memset/memcpy/memmove to vector instructions on ARM where the alignment permits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143582 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-02 22:52:45 +00:00
Chad Rosier
e07cd5e40a Add support for comparing integer non-legal types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143559 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-02 18:08:25 +00:00
Nick Lewycky
6a7efcfc02 Always use the string pool, even when it makes the .o larger. This may help 
tools that read the debug info in the .o files by making the DIE sizes more
consistent.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143186 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 05:29:47 +00:00
Jakob Stoklund Olesen
b0117eed84 Also set addrmode6 alignment when align==size. 
Previously, we were only setting the alignment bits on over-aligned
loads and stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143160 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-27 22:39:16 +00:00