6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-24 06:30:19 +00:00
Code Issues Projects Releases Wiki Activity
34,020 Commits 39 Branches 0 Tags 277 MiB
3e20bba5eb
Commit Graph

34 Commits

Author SHA1 Message Date
Evan Cheng
102dc195b6 No need for noResults anymore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40075 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-20 00:21:23 +00:00
Evan Cheng
64d80e3387 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-19 01:14:50 +00:00
Evan Cheng
88cc092ca5 Try committing again. Add OptionalDefOperand. Remove clobbersPred. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38498 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-10 18:05:01 +00:00
Dan Gohman
d45eddd214 Revert the earlier change that removed the M_REMATERIALIZABLE machine 
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37728 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-26 00:48:07 +00:00
Dan Gohman
82a87a0172 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad 
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37644 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-19 01:48:05 +00:00
Evan Cheng
eaa91b0a1f Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37643 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-19 01:26:51 +00:00
Evan Cheng
b5c1c9c8e3 Add clobbersPred - instruction that clobbers condition code / register which are used to predicate instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37465 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-06 10:14:55 +00:00
Evan Cheng
5127ce09a4 Rename M_PREDICATED to M_PREDICABLE; opcode can be specified isPredicable without having a PredicateOperand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37116 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 20:45:24 +00:00
Evan Cheng
04677a3b49 Recognize target instruction flag 'isReMaterializable'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35159 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 06:20:37 +00:00
Chris Lattner
f64f9a4b75 Remove the isTwoAddress property from the CodeGenInstruction class. It should 
not be used for anything other than backwards compat constraint handling.

Add support for a new DisableEncoding property which contains a list of
registers that should not be encoded by the generated code emitter.  Convert
the codeemitter generator to use this, fixing some PPC JIT regressions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31769 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-15 23:23:02 +00:00
Chris Lattner
0bb75004ff ADd support for adding constraints to suboperands 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31748 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-15 02:38:17 +00:00
Chris Lattner
a0cca4ae26 simplify the way operand flags and constraints are handled, making it easier 
to extend.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31481 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-06 23:49:51 +00:00
Chris Lattner
a818e92f8b recognize ppc's blr instruction as predicated 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31480 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-06 21:44:54 +00:00
Jeff Cohen
d41b30def3 Unbreak VC++ build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31464 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-05 19:31:28 +00:00
Evan Cheng
e2ba897588 Add operand constraints to TargetInstrInfo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31333 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-01 00:27:05 +00:00
Evan Cheng
51fecc80f7 * Remove instruction fields hasInFlag / hasOutFlag and added SNDPInFlag and 
SNDPOutFlag to DAG nodes. These properties do not belong to target specific
instructions.
* Added DAG node property SNDPOptInFlag. It's same as SNDPInFlag except it's
optional. Used by ret / call, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25154 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-09 18:27:06 +00:00
Evan Cheng
2b4ea795a2 Added field noResults to Instruction. 
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25017 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-26 09:11:45 +00:00
Evan Cheng
7b05bd5814 * Support for hasInFlag and hasOutFlag (on instructions). Remove nameless FLAG 
support which is fragile.
* Fixed a number of bugs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24996 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-23 22:11:47 +00:00
Evan Cheng
1c3d19eb15 * Commit the fix (by Chris) for a tblgen type inferencing bug. 
* Enhanced tblgen to handle instructions which have chain operand and writes a
chain result.
* Enhanced tblgen to handle instructions which produces no results. Part of
the change is a temporary hack which relies on instruction property (e.g.
isReturn, isBranch). The proper fix would be to change the .td syntax to
separate results dag from ops dag.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24587 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-04 08:18:16 +00:00
Nate Begeman
86193d1190 Nuke CodeGenInstruction's ValueType member, it is no longer used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24556 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-01 00:12:04 +00:00
Nate Begeman
8ef9d16d39 fit into 80 columns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24554 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-30 23:58:18 +00:00
Chris Lattner
65303d6bd7 Teach tblgen about instruction operands that have multiple MachineInstr 
operands, digging into them to find register values (used on X86).  Patch
by Evan Cheng!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24424 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-19 07:05:57 +00:00
Chris Lattner
5f89bf0f9d spell this variable right 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23095 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-26 20:42:52 +00:00
Chris Lattner
8b50f9b8dc Expose a new flag to TargetInstrInfo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23094 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-26 20:40:46 +00:00
Chris Lattner
0e384b66a7 For now, just emit empty operand info structures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22910 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-19 16:57:28 +00:00
Chris Lattner
cfbf96aa9c Figure out how many operands each instruction has, keep track of whether 
or not it's variable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22885 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 23:38:41 +00:00
Misha Brukman
3da94aec4d Remove trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21428 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-22 00:00:37 +00:00
Chris Lattner
aad75aa1a2 Expose isConvertibleToThreeAddress and isCommutable bits to the code generator. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19243 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-02 02:29:04 +00:00
Nate Begeman
cdd66b524f Add support for the isLoad and isStore flags, needed by the instruction scheduler 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16554 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-28 21:01:45 +00:00
Chris Lattner
5b71d3af35 Turn the hasDelaySlot flag into the M_DELAY_SLOT_FLAG 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16553 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-28 18:38:01 +00:00
Chris Lattner
175580c0f3 Make the AsmWriter a first-class tblgen object. Allow targets to specify 
name of the generated asmwriter class, and the name of the format string.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15747 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-14 22:50:53 +00:00
Chris Lattner
cf03da0ce9 Start parsing more information from the Operand information 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15644 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-11 02:22:39 +00:00
Chris Lattner
87c5905e0b Parse the operand list of the instruction. We currently support register and immediate operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15390 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-01 07:42:39 +00:00
Chris Lattner
ec3524064c Add, and start using, the CodeGenInstruction class. This class represents 
an instance of the Instruction tablegen class.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15385 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-01 05:04:00 +00:00