Commit Graph

108041 Commits

Author SHA1 Message Date
Frederic Riss
69513f19ba Fix a non-virtual destructor warning introduced in r217747.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217756 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 10:38:13 +00:00
Chandler Carruth
04402a6c13 [x86] Undo a flawed transform I added to form UNPCK instructions when
AVX is available, and generally tidy up things surrounding UNPCK
formation.

Originally, I was thinking that the only advantage of PSHUFD over UNPCK
instruction variants was its free copy, and otherwise we should use the
shorter encoding UNPCK instructions. This isn't right though, there is
a larger advantage of being able to fold a load into the operand of
a PSHUFD. For UNPCK, the operand *must* be in a register so it can be
the second input.

This removes the UNPCK formation in the target-specific DAG combine for
v4i32 shuffles. It also lifts the v8 and v16 cases out of the
AVX-specific check as they are potentially replacing multiple
instructions with a single instruction and so should always be valuable.
The floating point checks are simplified accordingly.

This also adjusts the formation of PSHUFD instructions to attempt to
match the shuffle mask to one which would fit an UNPCK instruction
variant. This was originally motivated to allow it to match the UNPCK
instructions in the combiner, but clearly won't now.

Eventually, we should add a MachineCombiner pass that can form UNPCK
instructions post-RA when the operand is known to be in a register and
thus there is no loss.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217755 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 10:35:41 +00:00
Chandler Carruth
a6cc351c5b [x86] Teach the new vector shuffle lowering to use 'punpcklwd' and
'punpckhwd' instructions when suitable rather than falling back to the
generic algorithm.

While we could canonicalize to these patterns late in the process, that
wouldn't help when the freedom to use them is only visible during
initial lowering when undef lanes are well understood. This, it turns
out, is very important for matching the shuffle patterns that are used
to lower sign extension. Fixes a small but relevant regression in
gcc-loops with the new lowering.

When I changed this I noticed that several 'pshufd' lowerings became
unpck variants. This is bad because it removes the ability to freely
copy in the same instruction. I've adjusted the widening test to handle
undef lanes correctly and now those will correctly continue to use
'pshufd' to lower. However, this caused a bunch of churn in the test
cases. No functional change, just churn.

Both of these changes are part of addressing a general weakness in the
new lowering -- it doesn't sufficiently leverage undef lanes. I've at
least a couple of patches that will help there at least in an academic
sense.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217752 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 09:02:37 +00:00
Frederic Riss
d090be97a8 Fix ambiguous typedef introduced in r217747.
Use fully qualified name inside a typedef from llvm::iterator_range<...> to
iterator_range. This is reported (rightly I think) by GCC as an
ambiguous name redefinition. Hope this fixes the buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217751 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 08:23:07 +00:00
David Majnemer
c3e70ca886 InstSimplify: Simplify trivial and/or of icmps
Some ICmpInsts when anded/ored with another ICmpInst trivially reduces
to true or false depending on whether or not all integers or no integers
satisfy the intersected/unioned range.

This sort of trivial looking code can come about when InstCombine
performs a range reduction-type operation on sdiv and the like.

This fixes PR20916.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217750 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 08:15:28 +00:00
Frederic Riss
740506d9ca Fix DebugInfo replaceAllUsesWith.
Summary:
replaceAllUsesWith had been modified to allow a DbgNode value to be
replaced by itself. In that case a new node is created by copying the
current DbgNode and the copy is used as replacement value.

When that copying happens, the value stored in this->DbgNode at the end
of RAUW would be a reference to the Node that has just been deleted.

This doesn't produce any bug right now, because the DI node on which we
call RAUW won't be used again.

Reviewers: dblaikie, echristo, aprantl

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5326

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217749 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 07:50:42 +00:00
Frederic Riss
04dc1486ac Move replaceAllUsesWith() from DIType to DIDescriptor.
RAUW was only used on DIType to merge declarations and full definitions
of types. In order to support the same functionality for functions and
global variables, move the function up type DI type hierarchy to the
common parent of DIType, DISubprogram and DIVariable which is
DIDescriptor.

This functionality will be exercized when we add the code to emit
imported declarations for forward declared function/variables.

Reviewers: echristo, dblaikie, aprantl

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5325

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217748 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 07:50:36 +00:00
Frederic Riss
ea3ce67d71 Introduce the DWARFUnitSection abstraction.
A DWARFUnitSection is the collection of Units that have been extracted from
the same debug section.

By embeding a reference to their DWARFUnitSection in each unit, the DIEs
will be able to resolve inter-unit references by interrogating their Unit's
DWARFUnitSection.

This is a minimal patch where the DWARFUnitSection is-a SmallVector of Units,
thus exposing exactly the same interface as before. Followup-up patches might
change from inheritance to composition in order to expose only the wanted
DWARFUnitSection abstraction.

    Differential Revision: http://reviews.llvm.org/D5310

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217747 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 07:50:27 +00:00
Justin Bogner
b1287f54cf llvm-cov: Clean up some redundancy in the view API (NFC)
This removes the need to pass a starting and ending line when creating
a SourceCoverageView, since these are easy to determine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217746 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 03:41:04 +00:00
Justin Bogner
baca001683 llvm-cov: Simplify CounterMappingRegion, pushing logic to its user
A single function in SourceCoverageDataManager was the only user of
some of the comparisons in CounterMappingRegion, and at this point we
know that only one file is relevant. This lets us use slightly simpler
logic directly in the client.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217745 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 03:41:01 +00:00
Chandler Carruth
e610c324e1 [x86] Teach the new vector shuffle lowering to use BLENDPS and BLENDPD.
These are super simple. They even take precedence over crazy
instructions like INSERTPS because they have very high throughput on
modern x86 chips.

I still have to teach the integer shuffle variants about this to avoid
so many domain crossings. However, due to the particular instructions
available, that's a touch more complex and so a separate patch.

Also, the backend doesn't seem to realize it can commute blend
instructions by negating the mask. That would help remove a number of
copies here. Suggestions on how to do this welcome, it's an area I'm
less familiar with.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217744 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-14 23:43:33 +00:00
NAKAMURA Takumi
0309c5d4bc llvm/test/CodeGen/X86/vec_shuffle-38.ll: Add explicit -mtriple=x86_64-unknown to avoid incompatibility of win32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217742 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-14 23:39:01 +00:00
Chandler Carruth
59def2bffa [x86] Add an SSE41 mode to this test. Nothing interesting here, its the
same as SSE3.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217741 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-14 23:28:12 +00:00
Chandler Carruth
151a867774 [x86] Switch this test to use an ALL prefix with special SSE2 and SSE3
variants where significant.

This will make it more obvious what is happening when we start using
blends in SSE41.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217740 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-14 23:19:37 +00:00
Chandler Carruth
85e37090e8 [x86] Add some test cases where we should emit blendpd in SSE4.1. No
actual change yet though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217739 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-14 23:15:52 +00:00
Chandler Carruth
33957173a7 [x86] Teach the vector combiner that picks a canonical shuffle from to
support transforming the forms from the new vector shuffle lowering to
use 'movddup' when appropriate.

A bunch of the cases where we actually form 'movddup' don't actually
show up in the test results because something even later than DAG
legalization maps them back to 'unpcklpd'. If this shows back up as
a performance problem, I'll probably chase it down, but it is at least
an encoded size loss. =/

To make this work, also always do this canonicalizing step for floating
point vectors where the baseline shuffle instructions don't provide any
free copies of their inputs. This also causes us to canonicalize
unpck[hl]pd into mov{hl,lh}ps (resp.) which is a nice encoding space
win.

There is one test which is "regressed" by this: extractelement-load.
There, the test case where the optimization it is testing *fails*, the
exact instruction pattern which results is slightly different. This
should probably be fixed by having the appropriate extract formed
earlier in the DAG, but that would defeat the purpose of the test.... If
this test case is critically important for anyone, please let me know
and I'll try to work on it. The prior behavior was actually contrary to
the comment in the test case and seems likely to have been an accident.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217738 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-14 22:41:37 +00:00
Yaron Keren
e1c77ca37a In DwarfEHPrepare, after all passes are run, RewindFunction may be a dangling
pointer to a dead function. To make sure it's valid, doFinalization nullptrs
RewindFunction just like the constructor and so it will be found on next run.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217737 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-14 20:36:28 +00:00
Matt Arsenault
a0ba49844c R600/SI: Fix broken check lines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217736 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-14 18:32:05 +00:00
James Molloy
4fb9bbe72f [A57FPLoadBalancing] Modify r217689 - actually we do need to check defs
... Just make sure we check uses first so we see the kill first. It
turns out ignoring defs gives some pretty nasty runtime failures.
I'm certain this is the fix but I'm still reducing a testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217735 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-14 18:24:26 +00:00
Juergen Ributzka
5bf1f01c15 [FastISel][AArch64] Add support for non-native types for logical ops.
Extend the logical ops selection to also support non-native types such as i1,
i8, and i16.

Fixes rdar://problem/18330589.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217732 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-13 23:46:28 +00:00
Nick Lewycky
c2104d4856 Add control of function merging to the PMBuilder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217731 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-13 21:46:00 +00:00
Matt Arsenault
75d7f73678 Fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217730 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-13 19:58:27 +00:00
Benjamin Kramer
e853a8665e Simplify code. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217726 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-13 12:38:49 +00:00
Chad Rosier
9f4b17d14a [AArch64] Update test case to pass with post-RA MI scheduler.
Check that the post RA scheduler is being skipped, regardless of
whether it's the top-down list latency scheduler or the post-RA
MI scheduler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217725 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-13 03:23:23 +00:00
Nick Kledzik
a77096bb53 [llvm-objdump] Use PRIX64 with format()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217724 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-13 00:18:40 +00:00
Nick Kledzik
2981a19485 Stop suppress error messages in test case to see why one buildbot is failing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217715 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-12 22:46:01 +00:00
Chad Rosier
995738064a [AArch64] Don't enable the post-RA MI scheduler at OptNone.
Hopefully, this will appease the bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217712 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-12 22:17:28 +00:00
Owen Anderson
00edf1f086 Allow targets to custom legalize vector insertion and extraction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217711 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-12 22:16:11 +00:00
Nick Kledzik
a240fc5cb9 [llvm-objdump] support -rebase option for mach-o to dump rebasing info
Similar to my previous -exports-trie option, the -rebase option dumps info from
the LC_DYLD_INFO load command. The rebasing info is a list of the the locations
that dyld needs to adjust if a mach-o image is not loaded at its preferred 
address. Since ASLR is now the default, images almost never load at their
preferred address, and thus need to be rebased by dyld.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217709 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-12 21:34:15 +00:00
Justin Bogner
824444e97a llvm-profdata: Avoid undefined behaviour when reading raw profiles
The raw profiles that are generated in compiler-rt always add padding
so that each profile is aligned, so we can simply treat files that
don't have this property as malformed.

Caught by Alexey's new ubsan bot. Thanks!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217708 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-12 21:22:55 +00:00
Owen Anderson
206359ba20 Remove an unnecessary restriction. MIsNeedChainEdge() should be checked even when scheduler AliasAnalysis is not
enabled.  A good chunk of the MIsNeedChainEdge() is logic that is valid and should be applied even for targets
that are not using for alias analysis.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217706 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-12 21:17:55 +00:00
Yaron Keren
0f39f35425 The MCAssembler.h include isn't used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217705 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-12 20:29:17 +00:00
Ehsan Akhgari
97688c4ee3 Add an overload of getLastArgNoClaim taking two OptSpecifiers.
Summary: This will be used in clang.

Test Plan: Will be tested on the clang side.

Reviewers: hansw

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5337

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217702 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-12 19:42:53 +00:00
Chad Rosier
9adca7fba6 FileCheckize. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217698 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-12 17:55:16 +00:00
JF Bastien
5223ff81f5 Add support for le64.
Summary:
le64 is a generic little-endian 64-bit processor, mimicking le32.

Depends on D5318.

Test Plan: make check-all

Reviewers: dschuff

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5319

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217697 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-12 17:54:17 +00:00
Chad Rosier
4fb3a966d0 [AArch64] Enable post-RA MI scheduler.
Phabricator Revision: http://reviews.llvm.org/D5278
Patch by Sanjin Sijaric!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217693 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-12 17:40:39 +00:00
James Molloy
ca332457ba [A57FPLoadBalancing] Remove support for vector types
Vector MUL/MLAs have tied operands, which gives us extra constraints
that we currently can't handle. Instead of silently doing the wrong
thing, remove support to be readded later properly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217690 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-12 16:55:32 +00:00
James Molloy
b4fbcbc288 [A57FPLoadBalancing] Ignore <def>s when checking if a chain may be killed.
Defs are seen before uses, so a def without the kill flag doesn't necessarily
mean that the register is not killed on that instruction. It may be killed
in a later use operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217689 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-12 16:55:26 +00:00
Jordan Rose
c919e57cbf [lit] Parse all strings as UTF-8 rather than ASCII.
As far as I can tell UTF-8 has been supported since the beginning of Python's
codec support, and it's the de facto standard for text these days, at least
for primarily-English text. This allows us to put Unicode into lit RUN lines.

rdar://problem/18311663

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217688 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-12 16:46:05 +00:00
NAKAMURA Takumi
81d53b7290 Move sys::fs::AccessMode out of @brief in the function. [-Wdocumentation]
FIXME: Annotate sys::fs::AccessMode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217685 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-12 15:12:32 +00:00
NAKAMURA Takumi
3b59cfdddc sys::fs::access(): Fix @param [-Wdocumentation]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217684 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-12 15:12:21 +00:00
NAKAMURA Takumi
35d9566e68 llvm/test/CodeGen/X86/vec_ctbits.ll: Add explicit -mtriple=x86_64-unknown. It was incompatible to Win32 x64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217683 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-12 15:10:56 +00:00
James Molloy
9204ab0456 [A57LoadBalancing] unique_ptr-ify.
Thanks to David Blakie for the in-depth review!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217682 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-12 14:35:17 +00:00
Zoran Jovanovic
614d8681e0 [mips][microMIPS] Implement JRADDIUSP instruction
Differential Revision: http://reviews.llvm.org/D5046


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217681 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-12 14:29:54 +00:00
Bill Schmidt
183704cb08 Address comments on r217622
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217680 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-12 14:26:36 +00:00
Zoran Jovanovic
7fd9d5636a [mips][microMIPS] Implement BGEZALS and BLTZALS instructions
Differential Revision: http://reviews.llvm.org/D5004


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217678 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-12 13:51:58 +00:00
Zoran Jovanovic
cf6da9bed3 [mips][microMIPS] Implement JALS and JALRS instructions.
Differential Revision: http://reviews.llvm.org/D5003


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217676 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-12 13:43:41 +00:00
Zoran Jovanovic
75449bc4d7 [mips][microMIPS] Implement TLBP, TLBR, TLBWI and TLBWR instructions
Differential Revision: http://reviews.llvm.org/D5211


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217675 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-12 13:33:33 +00:00
James Molloy
94c25519a2 [ARM] Teach the cost model that cross-class copies are costly.
Cross-class copies being expensive is actually a trait of the microarchitecture, but as I haven't yet seen an example of a microarchitecture where they're cheap it seems best to just enable this by default, covering the non-mcpu build case.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217674 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-12 13:29:40 +00:00
Benjamin Kramer
66feb63c3c Legalizer: Use the scalar bit width when promoting bit counting instrs on
vectors.

e.g. when promoting ctlz from <2 x i32> to <2 x i64> we have to fixup
the result by 32 bits, not 64. PR20917.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217671 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-12 12:50:27 +00:00