Commit Graph

2426 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
b95fd2d5fd Tweak hash function and compress hash tables.
Make the hash tables as small as possible while ensuring that all
lookups can be done in less than 8 probes.

Cut the aliases hash table in half by only storing a < b pairs - it
is a symmetric relation.

Use larger multipliers on the initial hash function to ensure that it
properly covers the whole table, and to resolve some clustering in the
very regular ARM register bank.

This reduces the size of most of these tables by 4x - 8x. For instance,
the ARM tables shrink from 48 KB to 8 KB.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132888 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-12 07:04:32 +00:00
Jakob Stoklund Olesen
bf710cc23e Remove now dead code.
These computations have been moved to CodeGenRegisters.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132887 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-12 07:04:28 +00:00
Jakob Stoklund Olesen
4091b059ec Extract the generateHashTable function.
The constant hash tables for sub-registers and overlaps are generated
the same way, so extract a function to generate and print the hash
table.

Also use the information computed by CodeGenRegisters.cpp instead of the
locally data.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132886 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-12 07:04:26 +00:00
Jakob Stoklund Olesen
026dc223ae Compute lists of sub-regs, super-regs, and overlapping regs.
Besides moving structural computations to CodeGenRegisters.cpp, this
also well-defines the order of these lists:

- Sub-register lists come from a pre-order traversal of the graph
  defined by the SubRegs lists in the .td files.

- Super-register lists are topologically ordered so no register comes
  before any of its sub-registers. When the sub-register graph is not a
  tree, independent super-registers appear in numerical order.

- Lists of overlapping registers are ordered according to register
  number.

This reverses the order of the super-regs lists, but nobody was
depending on that. The previous order of the overlaps lists was odd, and
it may have depended on the precise behavior of std::stable_sort.

The old computations are still there, but will be removed shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132881 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-12 03:05:52 +00:00
Jakob Stoklund Olesen
b5923db192 Move the list of registers into CodeGenRegBank.
Also move the sub-register index computations from RegisterInfoEmitter
into CodeGenRegBank.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132865 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-11 00:28:06 +00:00
Jakob Stoklund Olesen
dc29c44713 Move some sub-register index calculations to CodeGenRegisters.cpp
Create a new CodeGenRegBank class that will eventually hold all the code
that computes the register structure from Records.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132849 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-10 18:40:00 +00:00
Jakob Stoklund Olesen
f1e2b23dfa Move TableGen's register bank classes to their own source file.
I'll be moving some more code there to gather all of the
register-specific stuff in one place. Currently it is shared between
CodeGenTarget and RegisterInfoEmitter.

The plan is that CodeGenRegisters can compute the full register bank
structure while RegisterInfoEmitter only will handle the printing part.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132788 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09 18:42:07 +00:00
Bob Wilson
e450a0046b Add special-case range checking for VCVT_N intrinsic immediate operands.
Radar 9558930.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132782 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09 16:57:29 +00:00
Chad Rosier
36a300ac02 Fixed a few illegal paths with llvm_unreachable. Patch by Cameron McInally.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132732 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-07 20:41:31 +00:00
Jakob Stoklund Olesen
c017bc1c1e Drop a RecordKeeper reference that wasn't necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132636 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-04 07:49:55 +00:00
Jakob Stoklund Olesen
1023f5a42d Silence compiler warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132624 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-04 05:09:36 +00:00
Jakob Stoklund Olesen
1de99829b6 Teach TableGen to evaluate DAG expressions as set operations.
A TableGen backend can define how certain classes can be expanded into
ordered sets of defs, typically by evaluating a specific field in the
record. The SetTheory class can then evaluate DAG expressions that refer
to these named sets.

A number of standard set and list operations are predefined, and the
backend can add more specialized operators if needed. The -print-sets
backend is used by SetTheory.td to provide examples.

This is intended to simplify how register classes are defined:

  def GR32_NOSP : RegisterClass<"X86", [i32], 32, (sub GR32, ESP)>;

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132621 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-04 04:11:37 +00:00
Nick Lewycky
b2afe8759d Rework the logic to not rely on undefined behaviour (1LL << 64). Also simplify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132537 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-03 08:25:39 +00:00
Jakob Stoklund Olesen
f462e3fac7 Make it possible to have unallocatable register classes.
Some register classes are only used for instruction operand constraints.
They should never be used for virtual registers. Previously, those
register classes were given an empty allocation order, but now you can
say 'let isAllocatable=0' in the register class definition.

TableGen calculates if a register is part of any allocatable register
class, and makes that information available in TargetRegisterDesc::inAllocatableClass.

The goal here is to eliminate use cases for overriding allocation_order_*
methods.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132508 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02 23:07:20 +00:00
Joerg Sonnenberger
dd137903e4 Add new -d option to tblgen. It writes a make(1)-style dependency file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132395 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01 13:10:15 +00:00
Bruno Cardoso Lopes
895c1e2dee Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value
must be encoded decremented by one. Only add encoding tests for ssat16
because ssat can't be parsed yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132324 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-31 03:33:27 +00:00
Rafael Espindola
6e032942cf Use the dwarf->llvm mapping to print register names in the cfi
directives.

Fixes PR9826.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132317 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-30 20:20:15 +00:00
Rafael Espindola
7a067cc6e0 Introduce the DwarfRegAlias class for declaring that two registers have the
same dwarf number. This will be used for creating a dwarf number to register
mapping.

The only case that needs this so far is the XMM/YMM registers that unfortunately
do have the same numbers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132314 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-30 17:49:59 +00:00
John McCall
bd0fa4c00d Change how tblgen generates attributes for intrinsics to use a single
switch.  With this newfound organization, teach tblgen how not to give
all intrinsics the 'nounwind' attribute.  Introduce a new intrinsic,
llvm.eh.resume, which does not have this attribute.  Documentation and uses
to follow.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132252 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28 06:31:34 +00:00
Rafael Espindola
7bf114c1bd Fix the root cause of the bootstrap failure:
There was no way to check if a given register/mode pair was valid. We now return
an error code (-2) instead of asserting. If anyone thinks that an assert
at this point  is really needed, we can autogen a hasValidDwarfRegNum instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132236 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28 00:13:01 +00:00
Argyrios Kyrtzidis
804cb23305 [tablegen] A couple of changes to ClangDiagnosticEmmitter.
-Emit an empty warning option as string ("") instead of 0.
-For diagnostic names also emit the size of the string.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132046 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 05:04:22 +00:00
Bill Wendling
f415d8b646 Use a more efficient data structure for the "operand map". The number of
operands to an instruction aren't great, so an iterative search is fairly quick
and doesn't have the overhead of std::map.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131886 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-23 00:18:33 +00:00
Cameron Zwarich
3a2d255ce6 Fix PR9947 by placing OPFL_MemRefs on the node using memory operands rather than
the root if there is only one such node. This leaves only 2 verifier failures in
the entire test suite when running "make check".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131677 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 21:13:30 +00:00
Jakob Stoklund Olesen
4bfc6fba78 Downgrade a tablegen warning to an error.
Ambiguous sub-register index compositions are OK as long as the backend writer
knows what he is doing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131134 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-10 17:52:59 +00:00
Mon P Wang
183c627d89 Fixed MC encoding for index_align for VLD1/VST1 (single element from one lane) for size 32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131085 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-09 17:47:27 +00:00
Jakob Stoklund Olesen
123cab9480 Teach TableGen to automatically generate missing SubRegIndex instances.
The RegisterInfo.td file should only specify the indexes that sources need to
refer to. The rest is inferred.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131058 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-07 21:22:39 +00:00
Jim Grosbach
5d754bfa32 Improve diagnostics for some parse errors. Not asserting when a user input
error is detected is a good thing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131005 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-06 18:47:45 +00:00
Jim Grosbach
96883ec700 ParseFile() may throw, so extend the try/catch to handle that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131004 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-06 18:39:28 +00:00
Mikhail Glushenkov
3a21c55a14 llvmc: Make it possible to provide an argument to (join).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130914 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-05 04:24:58 +00:00
Jim Grosbach
b9d5af05fd Tidy up. Add missing newline to generated file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130779 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03 19:09:56 +00:00
Eli Friedman
206a10cf28 Filter out pattterns from the FastISel emitter which it doesn't actually know how to handle. No significant functionality change at the moment, but it's necessary for some changes I'm planning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130547 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-29 21:58:31 +00:00
Owen Anderson
4cdcb4772d Fix a bug in tblgen that caused incorrect encodings on instructions that specified operands with "bit" instead of "bits<1>".
Unfortunately, my only testcase for this is fragile, and the ARM AsmParser can't round trip the instruction in question.
<rdar://problem/9345702>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130410 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-28 17:51:45 +00:00
Mikhail Glushenkov
4e699cf518 Add a TODO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130092 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-24 14:17:41 +00:00
Jay Foad
ddcdcc8863 Remove unused STL header includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130068 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-23 19:53:52 +00:00
Johnny Chen
597fa65373 Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) should
print out ldr, not ldr.n.

rdar://problem/9267772


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130008 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-22 19:12:43 +00:00
Bob Wilson
c1fe100f35 Define Neon load/store intrinsics for Clang as macros instead of functions.
This is needed so the front-end can see "aligned" attributes on the type
for the pointer arguments.  Radar 9311427.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129964 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-22 00:37:01 +00:00
Jakob Stoklund Olesen
69ba413057 Don't allow per-register spill size and alignment.
These values were not used for anything. Spill size and alignment is a property
of the register class, not the register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129906 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-21 03:43:21 +00:00
Jakob Stoklund Olesen
6bfba2e5af Prefer cheap registers for busy live ranges.
On the x86-64 and thumb2 targets, some registers are more expensive to encode
than others in the same register class.

Add a CostPerUse field to the TableGen register description, and make it
available from TRI->getCostPerUse. This represents the cost of a REX prefix or a
32-bit instruction encoding required by choosing a high register.

Teach the greedy register allocator to prefer cheap registers for busy live
ranges (as indicated by spill weight).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129864 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20 18:19:48 +00:00
Eric Christopher
721ef66d17 Invert the meaning of printAliasInstr's return value. It now returns
true on success and false on failure. Update callers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129722 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-18 21:28:11 +00:00
Owen Anderson
57557155c9 Enhance the fixed-length disassembler to support the callbacks necessary for symbolic disassembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129708 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-18 18:42:26 +00:00
Chris Lattner
202a7a1e3f Add a new bit that ImmLeaf's can opt into, which allows them to duck out of
the generated FastISel.  X86 doesn't need to generate code to match ADD16ri8 
since ADD16ri will do just fine.  This is a small codesize win in the generated
instruction selector.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129692 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-18 06:36:55 +00:00
Chris Lattner
1518afddea Implement major new fastisel functionality: the matcher can now handle immediates with
value constraints on them (when defined as ImmLeaf's).  This is particularly important
for X86-64, where almost all reg/imm instructions take a i64immSExt32 immediate operand,
which has a value constraint.  Before this patch we ended up iseling the examples into
such amazing code as:

	movabsq	$7, %rax
	imulq	%rax, %rdi
	movq	%rdi, %rax
	ret

now we produce:

	imulq	$7, %rdi, %rax
	ret

This dramatically shrinks the generated code at -O0 on x86-64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129691 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-18 06:22:33 +00:00
Chris Lattner
9bfd5f3b22 introduce a new OpKind abstraction which wraps up operand flavors in a tidy little wrapper.
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129680 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-17 23:29:05 +00:00
Chris Lattner
a90dbc133f change OperandsSignature to use SmallVector<char> instead of std::vector<string>
since the strings are always exactly one character, and there are usually only 2-3 operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129678 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-17 22:24:13 +00:00
Chris Lattner
4447d6506c since the VT is fixed for a ImmLeaf, there is no reason to expose it to the matching code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129677 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-17 22:17:27 +00:00
Chris Lattner
7ed1391ff6 now that predicates have a decent abstraction layer on them, introduce a new
kind of predicate: one that is specific to imm nodes.  The predicate function
specified here just checks an int64_t directly instead of messing around with
SDNode's.  The virtue of this is that it means that fastisel and other things
can reason about these predicates.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-17 22:05:17 +00:00
Chris Lattner
543790673c Rework our internal representation of node predicates to expose more
structure and fix some fixmes.  We now have a TreePredicateFn class
that handles all of the decoding of these things.  This is an internal
cleanup that has no impact on the code generated by tblgen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129670 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-17 21:38:24 +00:00
Chris Lattner
461cd70311 remove some debugging code I added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129668 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-17 21:36:19 +00:00
Chris Lattner
602fc06817 1. merge fast-isel-shift-imm.ll into fast-isel-x86-64.ll
2. implement rdar://9289501 - fast isel should fold trivial multiplies to shifts
3. teach tblgen to handle shift immediates that are different sizes than the 
   shifted operands, eliminating some code from the X86 fast isel backend.
4. Have FastISel::SelectBinaryOp use (the poorly named) FastEmit_ri_ function
   instead of FastEmit_ri to simplify code.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129666 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-17 20:23:29 +00:00
Douglas Gregor
4954e9f2d9 Initial work to improve documentation for Clang's diagnostics, from Matthieu Monrocq
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129613 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15 22:04:07 +00:00