Commit Graph

2428 Commits

Author SHA1 Message Date
Duncan Sands
419cafb9fb Silence the compiler warning differently. The
original method caused gcc-4.2 to complain.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51186 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-16 09:19:16 +00:00
Nate Begeman
b434513a20 Actually scalarize the operand to BIT_CONVERT instead of asking someone to do
something with a v1 type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51160 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-15 20:40:58 +00:00
Dan Gohman
041e2eb517 IR support for extractvalue and insertvalue instructions. Also, begin
moving toward making structs and arrays first-class types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51157 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-15 19:50:34 +00:00
Evan Cheng
f0df03134e Make use of vector load and store operations to implement memcpy, memmove, and memset. Currently only X86 target is taking advantage of these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51140 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-15 08:39:06 +00:00
Evan Cheng
97e60d9e8c Use a better idiom to silence compiler warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51131 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-14 21:08:07 +00:00
Evan Cheng
3521334467 Really silence compiler warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51126 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-14 20:29:30 +00:00
Evan Cheng
b2031145e3 Really silence compiler warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51123 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-14 20:26:35 +00:00
Evan Cheng
5087124721 Silence some compiler warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51115 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-14 20:07:51 +00:00
Dan Gohman
d64a78c9ed When bit-twiddling CondCode values for integer comparisons produces
SETOEQ, is it does with (SETEQ & SETULE), map it to SETEQ.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51112 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-14 18:17:09 +00:00
Dan Gohman
9c78a39907 Whitespace cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51089 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-14 00:43:10 +00:00
Evan Cheng
77f0b7a50a Instead of a vector load, shuffle and then extract an element. Load the element from address with an offset.
pshufd $1, (%rdi), %xmm0
        movd %xmm0, %eax
=>
        movl 4(%rdi), %eax


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51026 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-13 08:35:03 +00:00
Dan Gohman
844731a7f1 Clean up the use of static and anonymous namespaces. This turned up
several things that were neither in an anonymous namespace nor static
but not intended to be global.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51017 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-13 00:00:25 +00:00
Nate Begeman
0d1704b955 Teach Legalize how to scalarize VSETCC
Teach X86 a few more vsetcc patterns.  Custom lowering for unsupported ones is next.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51009 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-12 23:09:43 +00:00
Evan Cheng
9bfa03c6fd Xform bitconvert(build_pair(load a, load b)) to a single load if the load locations are at the right offset from each other.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51008 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-12 23:04:07 +00:00
Evan Cheng
ad4196b44a Refactor isConsecutiveLoad from X86 to TargetLowering so DAG combiner can make use of it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50991 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-12 19:56:52 +00:00
Nate Begeman
b43e9c1965 Add support for vicmp/vfcmp codegen, more legalize support coming.
This is necessary to unbreak the build.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50988 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-12 19:40:03 +00:00
Dan Gohman
9ab9ee8209 Fix a missing break in the ISD::FLT_ROUNDS_ handling. Patch by giuma!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50967 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-12 16:07:15 +00:00
Anton Korobeynikov
0b12ecf6ff Turn StripPointerCast() into a method
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50836 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-07 22:54:15 +00:00
Dan Gohman
42ac929ed9 Fix a bug in the ComputeMaskedBits logic for multiply.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50793 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-07 00:35:55 +00:00
Anton Korobeynikov
b04adddd50 Make StripPointerCast a common function (should we mak it method of Value instead?)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50775 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-06 22:52:30 +00:00
Dan Gohman
4a3f6c8882 Make several variable declarations static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50696 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-06 01:53:16 +00:00
Dan Gohman
54eed37131 Instead of enumerating each opcode that isn't handled that
ComputeMaskedBits handles, just use a 'default:'. This avoids
TargetLowering's list getting out of date with SelectionDAG's.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50693 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-06 00:53:29 +00:00
Dan Gohman
23e1df8b8d Correct the value of LowBits in srem and urem handling in
ComputeMaskedBits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50692 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-06 00:51:48 +00:00
Mon P Wang
63307c335a Added addition atomic instrinsics and, or, xor, min, and max.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50663 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-05 19:05:59 +00:00
Dan Gohman
1d9cd50677 Fix a mistake in the computation of leading zeros for udiv.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50591 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-02 21:30:02 +00:00
Dan Gohman
7ceda160b3 Fix a typo in a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50562 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-02 00:05:03 +00:00
Dan Gohman
1fa850bdd2 Use push_back(...) instead of resize(1, ...), per review feedback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50561 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-02 00:03:54 +00:00
Dan Gohman
cba3b44d25 Fix uninitialized uses of the FPC variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50558 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-01 23:40:44 +00:00
Chris Lattner
6bf30ab347 don't randomly miscompile seto/setuo just because we are in
ffastmath mode.  This fixes rdar://5902801, a miscompilation
of gcc.dg/builtins-8.c.

Bill, please pull this into Tak.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50523 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-01 07:26:11 +00:00
Arnold Schwaighofer
30e62c098b Tail call optimization improvements:
Move platform independent code (lowering of possibly overwritten
arguments, check for tail call optimization eligibility) from
target X86ISelectionLowering.cpp to TargetLowering.h and
SelectionDAGISel.cpp.

Initial PowerPC tail call implementation:

Support ppc32 implemented and tested (passes my tests and
test-suite llvm-test).  
Support ppc64 implemented and half tested (passes my tests).
On ppc tail call optimization is performed if 
  caller and callee are fastcc
  call is a tail call (in tail call position, call followed by ret)
  no variable argument lists or byval arguments
  option -tailcallopt is enabled
Supported:
 * non pic tail calls on linux/darwin
 * module-local tail calls on linux(PIC/GOT)/darwin(PIC)
 * inter-module tail calls on darwin(PIC)
If constraints are not met a normal call will be emitted.

A test checking the argument lowering behaviour on x86-64 was added.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50477 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-30 09:16:33 +00:00
Scott Michel
82747a5484 Fix custom target lowering for zero/any/sign_extend: make sure that
DAG.UpdateNodeOperands() is called before (not after) the call to
TLI.LowerOperation().


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50461 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-30 00:26:38 +00:00
Roman Levenstein
a0201d5204 Use std::set instead of std::priority_queue for the RegReductionPriorityQueue.
This removes the existing bottleneck related to the removal of elements from 
the middle of the queue.

Also fixes a subtle bug in ScheduleDAGRRList::CapturePred:
It was updating the state of the SUnit before removing it. As a result, the
comparison operators were working incorrectly and this SUnit could not be removed 
from the queue properly.

Reviewed by Evan and Dan. Approved by Dan.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50412 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-29 09:07:59 +00:00
Chris Lattner
3fb2968f2f make the vector conversion magic handle multiple results.
We now compile test2/test3 to:

_test2:
	## InlineAsm Start
	set %xmm0, %xmm1
	## InlineAsm End
	addps	%xmm1, %xmm0
	ret
_test3:
	## InlineAsm Start
	set %xmm0, %xmm1
	## InlineAsm End
	paddd	%xmm1, %xmm0
	ret

as expected.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50389 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-29 04:48:56 +00:00
Chris Lattner
41f6259a4b add support for multiple return values in inline asm. This is a step
towards PR2094.  It now compiles the attached .ll file to:

_sad16_sse2:
	movslq	%ecx, %rax
	## InlineAsm Start
	%ecx %rdx %rax %rax %r8d %rdx %rsi
	## InlineAsm End
	## InlineAsm Start
	set %eax
	## InlineAsm End
	ret

which is pretty decent for a 3 output, 4 input asm.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50386 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-29 04:29:54 +00:00
Evan Cheng
33bf38ad88 Fix a bug in RegsForValue::getCopyToRegs() that causes cyclical scheduling units. If it's creating multiple CopyToReg nodes that are "flagged" together, it should not create a TokenFactor for it's chain outputs:
c1, f1 = CopyToReg                                                                                                                                                                                             
c2, f2 = CopyToReg                                                                                                                                                                                             
c3     = TokenFactor c1, c2                                                                                                                                                                                    
 ...                                                                                                                                                                                                                      
       = user c3, ..., f2

Now that the two CopyToReg's and the user are "flagged" together. They effectively forms a single scheduling unit. The TokenFactor is now both an operand and a successor of the Flagged nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50376 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28 22:07:13 +00:00
Dan Gohman
187db7b950 Evan pointed out that folding sext to zext may not be correct
if the zext is not legal.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50368 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28 18:47:17 +00:00
Dan Gohman
ebc3a3a3b2 Delete an unused constructor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50367 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28 18:28:49 +00:00
Dan Gohman
10a6b7ab65 Add a comment to CreateRegForValue that clarifies the handling of
aggregate types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50366 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28 18:19:43 +00:00
Dan Gohman
0fe00906c8 Rewrite the comments for RegsForValue and its members, and
reorder some of the members for clarity.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50365 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28 18:10:39 +00:00
Dan Gohman
b20d4f8d49 Don't call size() on each iteration of the loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50361 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28 17:42:03 +00:00
Dan Gohman
1f13c686df Fix the SVOffset values for loads and stores produced by
memcpy/memset expansion. It was a bug for the SVOffset value
to be used in the actual address calculations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50359 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28 17:15:20 +00:00
Dan Gohman
23e8b71526 Teach InstCombine's ComputeMaskedBits what SelectionDAG's
ComputeMaskedBits knows about cttz, ctlz, and ctpop. Teach
SelectionDAG's ComputeMaskedBits what InstCombine's knows
about SRem. And teach them both some things about high bits
in Mul, UDiv, URem, and Sub. This allows instcombine and
dagcombine to eliminate sign-extension operations in
several new cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50358 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28 17:02:21 +00:00
Dan Gohman
8f0ad582e8 Teach DAGCombine to convert (sext x) to (zext x) when the
sign-bit of x is known to be zero.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50357 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28 16:58:24 +00:00
Chris Lattner
6833b0601b Another collection of random cleanups. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50341 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28 07:16:35 +00:00
Chris Lattner
b606dba13b Remove the SmallVector ctor that converts from a SmallVectorImpl. This
conversion open the door for many nasty implicit conversion issues, and
can be easily solved by initializing with (V.begin(), V.end()) when 
needed.

This patch includes many small cleanups for sdisel also.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50340 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28 06:44:42 +00:00
Chris Lattner
8eaff0449c switch RegsForValue::Regs to be a SmallVector to avoid
heap thrash on tiny (usually single-element) vectors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50335 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28 06:02:19 +00:00
Chris Lattner
f899fce0c0 move static function out of anon namespace, no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50330 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-27 23:48:12 +00:00
Chris Lattner
acf8b01fd6 Another step to getting multiple result inline asm to work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50329 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-27 23:44:28 +00:00
Chris Lattner
24e1a9d311 typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50316 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-27 01:49:46 +00:00
Chris Lattner
5a09690446 Implement a signficant optimization for inline asm:
When choosing between constraints with multiple options,
like "ir", test to see if we can use the 'i' constraint and
go with that if possible.  This produces more optimal ASM in
all cases (sparing a register and an instruction to load it),
and fixes inline asm like this:

void test () {
  asm volatile (" %c0 %1 " : : "imr" (42), "imr"(14));
}

Previously we would dump "42" into a memory location (which
is ok for the 'm' constraint) which would cause a problem
because the 'c' modifier is not valid on memory operands.

Isn't it great how inline asm turns 'missed optimization'
into 'compile failed'??

Incidentally, this was the todo in 
PowerPC/2007-04-24-InlineAsm-I-Modifier.ll

Please do NOT pull this into Tak.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50315 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-27 00:37:18 +00:00