llvm-6502/lib/CodeGen/SelectionDAG
Chris Lattner 3fb2968f2f make the vector conversion magic handle multiple results.
We now compile test2/test3 to:

_test2:
	## InlineAsm Start
	set %xmm0, %xmm1
	## InlineAsm End
	addps	%xmm1, %xmm0
	ret
_test3:
	## InlineAsm Start
	set %xmm0, %xmm1
	## InlineAsm End
	paddd	%xmm1, %xmm0
	ret

as expected.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50389 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-29 04:48:56 +00:00
..
CallingConvLower.cpp
DAGCombiner.cpp
LegalizeDAG.cpp
LegalizeTypes.cpp
LegalizeTypes.h
LegalizeTypesExpand.cpp
LegalizeTypesFloatToInt.cpp
LegalizeTypesPromote.cpp
LegalizeTypesScalarize.cpp
LegalizeTypesSplit.cpp
Makefile
ScheduleDAG.cpp
ScheduleDAGList.cpp
ScheduleDAGRRList.cpp
SelectionDAG.cpp
SelectionDAGISel.cpp make the vector conversion magic handle multiple results. 2008-04-29 04:48:56 +00:00
SelectionDAGPrinter.cpp
TargetLowering.cpp