Commit Graph

87 Commits

Author SHA1 Message Date
Andrew Trick
ff7e4b11b1 Disabled subregister copy coalescing during MachineCSE.
This effectively backs out r197465 but leaves some of the general
fixes in place. Not all targets are ready to handle this feature. To
enable it, some infrastructure work is needed to better handle
register class constraints.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197514 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-17 19:29:36 +00:00
Andrew Trick
c4c5a1d526 Allow MachineCSE to coalesce trivial subregister copies the same way that it coalesces normal copies.
Without this, MachineCSE is powerless to handle redundant operations with truncated source operands.

This required fixing the 2-addr pass to handle tied subregisters. It isn't clear what combinations of subregisters can legally be tied, but the simple case of truncated source operands is now safely handled:

     %vreg11<def> = COPY %vreg1:sub_32bit; GR32:%vreg11 GR64:%vreg1
     %vreg12<def> = COPY %vreg2:sub_32bit; GR32:%vreg12 GR64:%vreg2
     %vreg13<def,tied1> = ADD32rr %vreg11<tied0>, %vreg12<kill>, %EFLAGS<imp-def>

Test case: cse-add-with-overflow.ll.

This exposed an existing bug in
PPCInstrInfo::commuteInstruction. Thanks to Rafael for the test case:
PowerPC/crash.ll.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197465 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-17 04:50:45 +00:00
Rafael Espindola
2eead9941a Revert "Allow MachineCSE to coalesce trivial subregister copies the same way that it coalesces normal copies."
This reverts commit r197414.

It broke the ppc64 bootstrap. I will post a testcase in a sec.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197424 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-16 20:57:09 +00:00
Andrew Trick
b961a26cec Allow MachineCSE to coalesce trivial subregister copies the same way
that it coalesces normal copies.

Without this, MachineCSE is powerless to handle redundant operations
with truncated source operands.

This required fixing the 2-addr pass to handle tied subregisters. It
isn't clear what combinations of subregisters can legally be tied, but
the simple case of truncated source operands is now safely handled:

     %vreg11<def> = COPY %vreg1:sub_32bit; GR32:%vreg11 GR64:%vreg1
     %vreg12<def> = COPY %vreg2:sub_32bit; GR32:%vreg12 GR64:%vreg2
     %vreg13<def,tied1> = ADD32rr %vreg11<tied0>, %vreg12<kill>, %EFLAGS<imp-def>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197414 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-16 19:36:21 +00:00
Andrew Trick
86d28968fd whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197413 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-16 19:36:18 +00:00
Craig Topper
a0ec3f9b7b Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186274 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-14 04:42:23 +00:00
Chandler Carruth
d04a8d4b33 Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03 16:50:05 +00:00
Manman Ren
39834da697 CSE: allow PerformTrivialCoalescing to check copies across basic block
boundaries.

Given the following case:
BB0
  %vreg1<def> = SUBrr %vreg0, %vreg7
  %vreg2<def> = COPY %vreg7
BB1
  %vreg10<def> = SUBrr %vreg0, %vreg2
We should be able to CSE between SUBrr in BB0 and SUBrr in BB1.

rdar://12462006


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168717 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-27 18:58:41 +00:00
Jakub Staszak
bb8ddc7e4f Don't use iterator after being erased.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168622 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-26 22:14:19 +00:00
Ulrich Weigand
b64e2115de Do not consider a machine instruction that uses and defines the same
physical register as candidate for common subexpression elimination
in MachineCSE.

This fixes a bug on PowerPC in MultiSource/Applications/oggenc/oggenc
caused by MachineCSE invalidly merging two separate DYNALLOC insns.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167855 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13 18:40:58 +00:00
Jakob Stoklund Olesen
feab72c20a Remove unused BitVectors from getAllocatableSet().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165999 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-16 00:05:06 +00:00
Jakob Stoklund Olesen
fb9ebbf236 Switch most getReservedRegs() clients to the MRI equivalent.
Using the cached bit vector in MRI avoids comstantly allocating and
recomputing the reserved register bit vector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165983 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 21:57:41 +00:00
Benjamin Kramer
5fa2d458af MachineCSE: Hoist isConstantPhysReg out of the loop, it checks for overlaps already.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161729 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-11 20:42:59 +00:00
Benjamin Kramer
cfc0ad6e48 PR13578: Teach MachineCSE that instructions that use a constant register can be CSE'd safely.
This is common e.g. when doing rip-relative addressing on x86_64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161728 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-11 19:05:13 +00:00
Manman Ren
39ad568c62 X86: enable CSE between CMP and SUB
We perform the following:
1> Use SUB instead of CMP for i8,i16,i32 and i64 in ISel lowering.
2> Modify MachineCSE to correctly handle implicit defs.
3> Convert SUB back to CMP if possible at peephole.

Removed pattern matching of (a>b) ? (a-b):0 and like, since they are handled
by peephole now.

rdar://11873276


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161462 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-08 00:51:41 +00:00
Manman Ren
ba86b13ad9 MachineCSE: Update the heuristics for isProfitableToCSE.
If the result of a common subexpression is used at all uses of the candidate
expression, CSE should not increase the live range of the common subexpression.

rdar://11393714 and rdar://11819721


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161396 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-07 06:16:46 +00:00
Bill Wendling
96cb112852 Remove tabs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160475 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-19 00:04:14 +00:00
Nick Lewycky
7a7a6db6d7 Remove ParentMap. You can just ask the domnode for its parent. No functionality
change.

Move the "Not profitable, avoid CSE!" debug message next to where we fail the
check for profitability and use a different message for avoiding CSE due to
being in different register classes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159729 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-05 06:19:21 +00:00
Jakob Stoklund Olesen
f152fe8d48 Switch some getAliasSet clients to MCRegAliasIterator.
MCRegAliasIterator can optionally visit the register itself, allowing
for simpler code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157837 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-01 20:36:54 +00:00
Craig Topper
e4fd907e72 Use uint16_t to store register overlaps to reduce static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152001 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04 10:43:23 +00:00
Jakob Stoklund Olesen
2129a0f677 Handle regmasks in MachineCSE.
Don't attempt to extend physreg live ranges across calls.

<rdar://problem/10942095>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151610 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28 02:08:50 +00:00
Lang Hames
c2e08db4e5 Re-enable 150652 and 150654 - Make FPSCR non-reserved, and make MachineCSE bail on reserved registers. This *should* be safe as of r150786.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150769 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-17 00:27:16 +00:00
Lang Hames
1834df8384 Oop - r150653 + r150654 broke one of my test cases. Backing out for now...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150655 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16 02:32:10 +00:00
Lang Hames
f7e31b9e81 MachineCSE shouldn't extend the live ranges of reserved or allocatable registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150653 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16 02:19:35 +00:00
Andrew Trick
1dd8c8560d Codegen pass definition cleanup. No functionality.
Moving toward a uniform style of pass definition to allow easier target configuration.
Globally declare Pass ID.
Globally declare pass initializer.
Use INITIALIZE_PASS consistently.
Add a call to the initializer from CodeGen.cpp.
Remove redundant "createPass" functions and "getPassName" methods.

While cleaning up declarations, cleaned up comments (sorry for large diff).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150100 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08 21:23:13 +00:00
Andrew Trick
1df91b0e54 whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150094 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08 21:22:43 +00:00
Duncan Sands
5b8a1db7ea Persuade GCC that there is nothing worth warning about here (there isn't).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149834 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05 14:20:11 +00:00
Evan Cheng
f96703e62f Avoid CSE of instructions which define physical registers across MBBs unless
the physical registers are not allocatable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147902 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11 00:38:11 +00:00
Evan Cheng
97b5beb7fe Allow machine-cse to look across MBB boundary when cse'ing instructions that
define physical registers. It's currently very restrictive, only catching
cases where the CE is in an immediate (and only) predecessor. But it catches
a surprising large number of cases.

rdar://10660865


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147827 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10 02:02:58 +00:00
Evan Cheng
5a96b3dad2 Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 07:15:52 +00:00
Bill Wendling
f6fb7ed53c We need to verify that the machine instruction we're using as a replacement for
our current machine instruction defines a register with the same register class
as what's being replaced. This showed up in the SPEC 403.gcc benchmark, where it
would ICE because a tail call was expecting one register class but was given
another. (The machine instruction verifier catches this situation.)
<rdar://problem/10270968>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141830 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 23:03:40 +00:00
Evan Cheng
e837dead3c - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28 19:10:37 +00:00
Eli Friedman
5e926ac651 Re-revert r130877; it's apparently causing a regression on 197.parser,
possibly related to cbnz formation.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130977 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-06 05:23:07 +00:00
Eli Friedman
5f6bf5d441 Minor correction to r130877; fixes PR9846 and hopefully the buildbot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130925 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-05 16:18:11 +00:00
Eli Friedman
baf717a08a Re-commit r130862 with a minor change to avoid an iterator running off the edge in some cases.
Original message:

Teach MachineCSE how to do simple cross-block CSE involving physregs.  This allows, for example, eliminating duplicate cmpl's on x86. Part of rdar://problem/8259436 .



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130877 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-04 22:10:36 +00:00
Eli Friedman
24d4c9911e Back out r130862; it appears to be breaking bootstrap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130867 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-04 20:48:42 +00:00
Eli Friedman
49cec1d818 Teach MachineCSE how to do simple cross-block CSE involving physregs. This allows, for example, eliminating duplicate cmpl's on x86. Part of rdar://problem/8259436 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130862 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-04 19:54:24 +00:00
Evan Cheng
cfea985f53 Fix a couple of places where changes are made but not tracked.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129287 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-11 18:47:20 +00:00
Chris Lattner
622a11bc07 fit in 80 cols and use MBB::isSuccessor instead of a hand
rolled std::find.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123164 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-10 07:51:31 +00:00
Jakob Stoklund Olesen
c9df025e33 Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.
These functions not longer assert when passed 0, but simply return false instead.

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123155 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-10 02:58:51 +00:00
Evan Cheng
c36b7069b4 Do not model all INLINEASM instructions as having unmodelled side effects.
Instead encode llvm IR level property "HasSideEffects" in an operand (shared
with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check
the operand when the instruction is an INLINEASM.

This allows memory instructions to be moved around INLINEASM instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123044 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-07 23:50:32 +00:00
Cameron Zwarich
53eeba586d Use a RecyclingAllocator to allocate values for MachineCSE's ScopedHashTable for
a 28% speedup of MachineCSE time on 403.gcc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122735 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-03 04:07:46 +00:00
Evan Cheng
a63cde26ff Teach machine cse to commute instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 22:16:21 +00:00
Evan Cheng
189c1ec4c1 Teach machine cse to eliminate instructions with multiple physreg uses and defs. rdar://8610857.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117745 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:36:03 +00:00
Owen Anderson
081c34b725 Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which
must be called in the pass's constructor.  This function uses static dependency declarations to recursively initialize
the pass's dependencies.

Clients that only create passes through the createFooPass() APIs will require no changes.  Clients that want to use the
CommandLine options for passes will need to manually call the appropriate initialization functions in PassInitialization.h
before parsing commandline arguments.

I have tested this with all standard configurations of clang and llvm-gcc on Darwin.  It is possible that there are problems
with the static dependencies that will only be visible with non-standard options.  If you encounter any crash in pass
registration/creation, please send the testcase to me directly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116820 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 17:21:58 +00:00
Owen Anderson
2ab36d3502 Begin adding static dependence information to passes, which will allow us to
perform initialization without static constructors AND without explicit initialization
by the client.  For the moment, passes are required to initialize both their
(potential) dependencies and any passes they preserve.  I hope to be able to relax
the latter requirement in the future.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116334 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 19:48:12 +00:00
Owen Anderson
ce665bd2e2 Now with fewer extraneous semicolons!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115996 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 22:25:06 +00:00
Jakob Stoklund Olesen
bf4699c561 Add MachineRegisterInfo::constrainRegClass and use it in MachineCSE.
This function is intended to be used when inserting a machine instruction that
trivially restricts the legal registers, like LEA requiring a GR32_NOSP
argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115875 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 23:54:39 +00:00
Evan Cheng
c2b768f09e Machine CSE was forgetting to clear some data structures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114222 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 21:59:42 +00:00
Evan Cheng
f437f73348 Fix a potential bug that can cause miscomparison with and without debug info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114220 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 21:56:26 +00:00