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41 Commits

Author SHA1 Message Date
Anton Korobeynikov
e56f9085b1 Add QPR_VFP2 regclass and add copy_to_regclass nodes, where needed to 
constraint the register usage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81635 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-12 22:21:08 +00:00
Anton Korobeynikov
6ca0b9e722 Add NEON 'laned' operations. This fixes another bunch of gcc testsuite fails and 
makes the code faster.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81220 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-08 15:22:32 +00:00
Evan Cheng
cdbb3f5d33 Fix PR4789. Teach eliminateFrameIndex how to handle VLDRQ and VSTRQ which cannot fold any immediate offset. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80191 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-27 01:23:50 +00:00
Chris Lattner
33adcfb4d2 rename TAI -> MAI, being careful not to make MAILJMP instructions :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79777 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-22 21:43:10 +00:00
Chris Lattner
af76e592c7 Rename TargetAsmInfo (and its subclasses) to MCAsmInfo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79763 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-22 20:48:53 +00:00
Devang Patel
24f20e0832 Record variable debug info at ISel time directly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79742 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-22 17:12:53 +00:00
Jim Grosbach
5aa1684e5d Add Thumb2 eh_sjlj_setjmp implementation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78701 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-11 19:42:21 +00:00
Jim Grosbach
cdc17ebc2b fix GetInstSizeInBytes for eh_sjlj_setjmp 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78683 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-11 17:08:15 +00:00
Jim Grosbach
764ab52dd8 Whitespace cleanup. Remove trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78666 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-11 15:33:49 +00:00
Evan Cheng
19068ba71a Add support for folding loads / stores into 16-bit moves used by Thumb2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78558 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-10 06:32:05 +00:00
Evan Cheng
2294645642 80 col violation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78557 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-10 05:51:48 +00:00
Anton Korobeynikov
baf31088f1 Use VLDM / VSTM to spill/reload 128-bit Neon registers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78468 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 13:35:48 +00:00
Evan Cheng
8fb903604e Code refactoring. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78455 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 03:20:32 +00:00
Evan Cheng
1d2426c470 Fix support to use NEON for single precision fp math. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78397 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-07 19:30:41 +00:00
Evan Cheng
861986401e It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing. 
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.

This fixes PR4659 and PR4682.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78361 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-07 00:34:42 +00:00
David Goodwin
7bfdca0206 When using NEON for single-precision FP, the NEON result must be placed in D0-D15 as these are the only D registers with S subregs. Introduce a new regclass to represent D0-D15 and use it in the NEON single-precision FP patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78244 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 21:02:22 +00:00
Chris Lattner
d90183d25d Move the getInlineAsmLength virtual method from TAI to TII, where 
the only real caller (GetFunctionSizeInBytes) uses it.

The custom ARM implementation of this is basically reimplementing
an assembler poorly for negligible gain.  It should be removed 
IMNSHO, but I'll leave that to ARMish folks to decide.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77877 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 05:20:37 +00:00
Evan Cheng
25f7cfc3cc Workaround a couple of Darwin assembler bugs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77781 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-01 06:13:52 +00:00
Evan Cheng
a0ee862f2e t2BR_JT is mov pc, it's 2 byte long, not 4. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77744 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 22:22:22 +00:00
Evan Cheng
d26b14c34c - Teach TBB / TBH offset limits are 510 and 131070 respectively since the offset 
is scaled by two.
- Teach GetInstSizeInBytes about TBB and TBH.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77701 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 18:28:05 +00:00
Evan Cheng
6495f63945 - More refactoring. This gets rid of all of the getOpcode calls. 
- This change also makes it possible to switch between ARM / Thumb on a
  per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
  using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77300 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 05:48:47 +00:00
Evan Cheng
78703ddafe convertToThreeAddress can't handle Thumb2 instructions (which don't have same address mode as ARM instructions). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77230 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 18:44:00 +00:00
Evan Cheng
83e0e36be8 Clean up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77221 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 18:25:24 +00:00
Evan Cheng
5ca53a7ad8 Get rid of some more getOpcode calls. 
This also fixes potential problems in ARMBaseInstrInfo routines not recognizing thumb1 instructions when 32-bit and 16-bit instructions mix.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77218 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 18:20:05 +00:00
Evan Cheng
1f5c988754 If CPSR is modified but the def is dead, then it's ok to fold the load / store. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77182 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 04:18:04 +00:00
Evan Cheng
5732ca084a Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate more getOpcode calls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77181 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 03:14:20 +00:00
Evan Cheng
08b93c6a70 Use the right instructions to copy between GPR and the more strictive tGPR classes. t2MOV does not match the RC requirements. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77175 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 00:33:08 +00:00
Evan Cheng
dced03fc84 Merge isLoadFromStackSlot into one since it behaves the same regardless of sub-target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77174 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 00:24:36 +00:00
Evan Cheng
68e3c6ae49 Just use a single isMoveInstr to catch all the cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77173 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 00:05:15 +00:00
Evan Cheng
66ac53165e Change Thumb2 jumptable codegen to one that uses two level jumps: 
Before:
      adr r12, #LJTI3_0_0
      ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
      .long    LBB3_24
      .long    LBB3_30
      .long    LBB3_31
      .long    LBB3_32

After:
      adr r12, #LJTI3_0_0
      add pc, r12, +r0, lsl #2
LJTI3_0_0:
      b.w    LBB3_24
      b.w    LBB3_30
      b.w    LBB3_31
      b.w    LBB3_32

This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
   (smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
   into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
   won't have to over-estimate the size.

Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77024 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-25 00:33:29 +00:00
Evan Cheng
789476240d Make sure thumb2 jumptable entries are aligned. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76986 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 18:20:44 +00:00
Eli Friedman
23ed52752b Remove unused member functions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76960 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 07:43:59 +00:00
Evan Cheng
b74bb1a7a4 FLDD, FLDS, FCPYD, FCPYS, FSTD, FSTS, VMOVD, VMOVQ maps to the same instructions on all sub-targets. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76925 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 00:53:56 +00:00
David Goodwin
5ff58b5c3a Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76919 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 00:16:18 +00:00
Anton Korobeynikov
b8e9ac834a Emit cross regclass register moves for thumb2. 
Minor code duplication cleanup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76124 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 23:26:06 +00:00
Torok Edwin
c23197a26f llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. 
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-14 16:55:14 +00:00
Torok Edwin
c25e7581b9 assert(0) -> LLVM_UNREACHABLE. 
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75379 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-11 20:10:48 +00:00
Evan Cheng
dd6f63209c 80 col violation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75358 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-11 06:37:27 +00:00
Evan Cheng
ab33150445 Move isPredicated from .cpp to .h 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75217 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-10 01:38:27 +00:00
Evan Cheng
e7cbe4118b Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75048 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 21:03:57 +00:00
David Goodwin
334c26473b Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75010 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 16:09:28 +00:00