Commit Graph

77061 Commits

Author SHA1 Message Date
Adam Nemet
718b023033 [LoopAccesses] Create the analysis pass
This is a function pass that runs the analysis on demand.  The analysis
can be initiated by querying the loop access info via LAA::getInfo.  It
either returns the cached info or runs the analysis.

Symbolic stride information continues to reside outside of this analysis
pass. We may move it inside later but it's not a priority for me right
now.  The idea is that Loop Distribution won't support run-time stride
checking at least initially.

This means that when querying the analysis, symbolic stride information
can be provided optionally.  Whether stride information is used can
invalidate the cache entry and rerun the analysis.  Note that if the
loop does not have any symbolic stride, the entry should be preserved
across Loop Distribution and LV.

Since currently the only user of the pass is LV, I just check that the
symbolic stride information didn't change when using a cached result.

On the LV side, LoopVectorizationLegality requests the info object
corresponding to the loop from the analysis pass.  A large chunk of the
diff is due to LAI becoming a pointer from a reference.

A test will be added as part of the -analyze patch.

Also tested that with AVX, we generate identical assembly output for the
testsuite (including the external testsuite) before and after.

This is part of the patchset that converts LoopAccessAnalysis into an
actual analysis pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229626 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 03:43:24 +00:00
Adam Nemet
0d1e8dd84e [LoopAccesses] Make blockNeedsPredication static
blockNeedsPredication is in LoopAccess in order to share it with the
vectorizer.  It's a utility needed by LoopAccess not strictly provided
by it but it's a good place to share it.  This makes the function static
so that it no longer required to create an LoopAccessInfo instance in
order to access it from LV.

This was actually causing problems because it would have required
creating LAI much earlier that LV::canVectorizeMemory().

This is part of the patchset that converts LoopAccessAnalysis into an
actual analysis pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229625 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 03:43:19 +00:00
Adam Nemet
14cc2e25c5 [LoopAccesses] Cache the result of canVectorizeMemory
LAA will be an on-demand analysis pass, so we need to cache the result
of the analysis.  canVectorizeMemory is renamed to analyzeLoop which
computes the result.  canVectorizeMemory becomes the query function for
the cached result.

This is part of the patchset that converts LoopAccessAnalysis into an
actual analysis pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229624 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 03:42:57 +00:00
Adam Nemet
8b0647f26b [LoopAccesses] Stash the report from the analysis rather than emitting it
The transformation passes will query this and then emit them as part of
their own report.  The currently only user LV is modified to do just
that.

This is part of the patchset that converts LoopAccessAnalysis into an
actual analysis pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229623 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 03:42:50 +00:00
Adam Nemet
eefec589e8 [LoopAccesses] Make VectorizerParams global
As LAA is becoming a pass, we can no longer pass the params to its
constructor.  This changes the command line flags to have external
storage.  These can now be accessed both from LV and LAA.

VectorizerParams is moved out of LoopAccessInfo in order to shorten the
code to access it.

This is part of the patchset that converts LoopAccessAnalysis into an
actual analysis pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229622 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 03:42:43 +00:00
Adam Nemet
38a9ebb065 [LoopAccesses] Rename LoopAccessAnalysis to LoopAccessInfo
LoopAccessAnalysis will be used as the name of the pass.

This is part of the patchset that converts LoopAccessAnalysis into an
actual analysis pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229621 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 03:42:35 +00:00
Akira Hatanaka
5506e22865 [InstCombine] Do not insert a GEP instruction before a landingpad instruction.
InstCombiner::visitGetElementPtrInst was using getFirstNonPHI to compute the
insertion point, which caused the verifier to complain when a GEP was inserted
before a landingpad instruction. This commit fixes it to use getFirstInsertionPt
instead.

rdar://problem/19394964


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229619 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 03:30:11 +00:00
Hal Finkel
8a85dee989 [BDCE] Don't forget uses of root instructions seen before the instruction itself
When visiting the initial list of "root" instructions (those which must always
be alive), for those that are integer-valued (such as invokes returning an
integer), we mark their bits as (initially) all dead (we might, obviously, find
uses of those bits later, but all bits are assumed dead until proven
otherwise). Don't do so, however, if we're already seen a use of those bits by
another root instruction (such as a store).

Fixes a miscompile of the sanitizer unit tests on x86_64.

Also, add a debug line for visiting the root instructions, and remove a debug
line which tried to print instructions being removed (printing dead
instructions is dangerous, and can sometimes crash).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229618 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 03:12:28 +00:00
Matt Arsenault
333507b7af R600/SI: Rename dst encoding field to be consistent with docs
The docs call this vdst instead of just dst.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229614 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 02:15:37 +00:00
Matt Arsenault
4fd9c8677c R600/SI: Consistently capitalize encoding field names
Some formats capitalized these, but most didn't. Change
them all to be consistently lowercase.

Now, non-encoding fields and convenience bits are capitalized.
Also remove weird looking empty line in some of the formats.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229613 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 02:15:35 +00:00
Matt Arsenault
85d96c94d6 R600/SI: Set noNamedPositionallyEncodedOperands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229612 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 02:15:32 +00:00
Matt Arsenault
abf19e5c1b R600/SI: Fix src1_modifiers for class instructions
src1 doesn't have modifiers, but the operand was missing
resulting in an encoding build error when all fields
are required.'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229611 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 02:15:30 +00:00
Matt Arsenault
5177e9551c R600/SI: Fix not setting clamp / omod for v_cndmask_b32_e64
Rename the multiclass since it now applies to the output
modifiers as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229610 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 02:15:27 +00:00
Matt Arsenault
b1beec140e R600: Fix operand encoding error
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229609 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 02:10:42 +00:00
Matt Arsenault
76f78b9ac2 R600/SI: Fix encoding error from glc bit on VI SMRD instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229608 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 02:10:40 +00:00
Matt Arsenault
9e39c99180 R600/SI: Fix operand encoding for flat instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229607 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 02:10:37 +00:00
Matt Arsenault
642c65e2df R600/SI: Fix error from vdst on no return atomics
Set the ignored field to 0 so we can enable
noNamedPositionallyEncodedOperands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229606 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 02:10:35 +00:00
Matt Arsenault
2422768a8a R600/SI: Add missing offset operand to buffer bothen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229605 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 02:04:38 +00:00
Matt Arsenault
fe524d5902 R600/SI: Add missing soffset operand to global atomics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229604 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 02:04:35 +00:00
Matt Arsenault
a0abb2055a R600/SI: Fix brace identation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229603 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 02:04:31 +00:00
Justin Bogner
09e5af7d61 Re-apply "InstrProf: Add unit tests for the profile reader and writer"
Have the InstrProfWriter return a MemoryBuffer instead of a
std::string. This fixes the alignment issues the reader would hit, and
it's a more appropriate type for this anyway.

I've also removed an ugly helper function that's not needed since
we're allowing initializer lists now, and updated some error code
checks based on MSVC's issues with r229473.

This reverts r229483, reapplying r229478.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229602 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 01:58:17 +00:00
Matthias Braun
62be98d510 LiveRangeCalc: Rename some parameters from kill to use, NFC.
Those parameters did not necessarily describe kill points but just uses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229601 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 01:50:52 +00:00
Sanjoy Das
00af5b5d50 Generalize getExtendAddRecStart to work with both sign and zero
extensions.

This change also removes `DEBUG(dbgs() << "SCEV: untested prestart
overflow check\n");` because that case has a unit test now.

Differential Revision: http://reviews.llvm.org/D7645



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229600 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 01:47:07 +00:00
Eric Christopher
3a7a58d6e0 Make the Mips AsmPrinter independent of global subtarget
initialization. Initialize the subtarget once per function and
migrate EmitStartOfAsmFile to either use calls on the
TargetMachine or get information from the subtarget we'd use
for assembling.

The top-level-ness of the MIPS attribute output for assembly is,
by nature, contrary to how we'd want to do this for an LTO
situation where we have multiple cpu architectures so this
solution is good enough for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229596 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 01:01:57 +00:00
Eric Christopher
68499a2f20 Unify selectMipsCPU implementations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229595 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 00:55:06 +00:00
Sanjoy Das
0afc9b33fe Bugfix: SCEV incorrectly marks certain expressions as nsw
I could not come up with a test case for this one; but I don't think
`getPreStartForSignExtend` can assume `AR` is `nsw` -- there is one
place in scalar evolution that calls `getSignExtendAddRecStart(AR,
...)` without proving that `AR` is `nsw`

(line 1564)

   OperandExtendedAdd =
     getAddExpr(WideStart,
                getMulExpr(WideMaxBECount,
                           getZeroExtendExpr(Step, WideTy)));
   if (SAdd == OperandExtendedAdd) {
     // If AR wraps around then
     //
     //    abs(Step) * MaxBECount > unsigned-max(AR->getType())
     // => SAdd != OperandExtendedAdd
     //
     // Thus (AR is not NW => SAdd != OperandExtendedAdd) <=>
     // (SAdd == OperandExtendedAdd => AR is NW)

     const_cast<SCEVAddRecExpr *>(AR)->setNoWrapFlags(SCEV::FlagNW);

     // Return the expression with the addrec on the outside.
     return getAddRecExpr(getSignExtendAddRecStart(AR, Ty, this),
                          getZeroExtendExpr(Step, Ty),
                          L, AR->getNoWrapFlags());
   }

Differential Revision: http://reviews.llvm.org/D7640



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229594 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 00:43:19 +00:00
Rafael Espindola
a12aeb0ac6 Twines should be passed by const ref.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229590 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-17 23:44:22 +00:00
Andrea Di Biagio
b3ff6a88b6 [X86][FastIsel] Teach how to select scalar integer to float/double conversions.
This patch teaches fast-isel how to select a (V)CVTSI2SSrr for an integer to 
float conversion, and how to select a (V)CVTSI2SDrr for an integer to double
conversion.

Added test 'fast-isel-int-float-conversion.ll'.

Differential Revision: http://reviews.llvm.org/D7698


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229589 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-17 23:40:58 +00:00
Rafael Espindola
3b75cfe179 Add r228939 back with a fix.
The problem in the original patch was not switching back to .text after printing
an eh table.

Original message:

On ELF, put PIC jump tables in a non executable section.

Fixes PR22558.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229586 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-17 23:34:51 +00:00
Sanjay Patel
4bf44517c8 rename variables again because these tables also deal with stores; NFC
Suggestion by Simon Pilgrim


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229574 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-17 22:38:06 +00:00
Duncan P. N. Exon Smith
54d7f09b71 IR: fieldIsMDNode() should be false for MDString
Simplify the code.  It has been a while since the schema has been so
"flexible".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229573 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-17 22:34:15 +00:00
Duncan P. N. Exon Smith
4c9121d5d9 AsmPrinter: Take range in DwarfExpression::AddExpression(), NFC
Previously `DwarfExpression::AddExpression()` relied on
default-constructing the end iterators for `DIExpression` -- once the
operands are represented explicitly via `MDExpression` (instead of via
the strange `StringRef` navigator in `DIHeaderIterator`) this won't
work.  Explicitly take an iterator for the end of the range.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229572 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-17 22:30:56 +00:00
Simon Pilgrim
cbc2ca5ec9 [X86][SSE] Generalised unpckl/unpckh shuffle matching
Added commuted unpckl/unpckh shuffle matching patterns as many cases containing undefined lanes fail to commute by themselves.

Differential Revision: http://reviews.llvm.org/D7564

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229571 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-17 22:24:32 +00:00
Sanjay Patel
0be02ef5b1 Add comment to explain a non-obvious setting; NFC.
This is paraphrased from Simon Pilgrim's comment in:
http://reviews.llvm.org/D7492



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229566 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-17 22:09:54 +00:00
Sanjay Patel
c3a976c935 remove function names from comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229558 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-17 21:55:20 +00:00
Sanjay Patel
a3a63972c5 replace meaningless variable names; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229549 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-17 21:37:28 +00:00
Rafael Espindola
e0a2541eb7 Add r228980 back.
Add support for having multiple sections with the same name and comdat.

Using this in combination with -ffunction-sections allows LLVM to output a .o
file with mulitple sections named .text. This saves space by avoiding long
unique names of the form .text.<C++ mangled name>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229541 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-17 20:48:01 +00:00
Rafael Espindola
84f0507260 Add r228889 back.
Original message:
Invert the section relocation map.

It now points from rel section to section. Use it to set sh_info, avoiding
a brittle name lookup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229539 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-17 20:40:59 +00:00
Rafael Espindola
8fd9fc3297 Add r228888 back.
Original message:

Use the existing SymbolTableIndex instead of doing a lookup. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229538 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-17 20:37:50 +00:00
Rafael Espindola
07102899ac Add r228886 back now that r229530 fixed the issue lldb was hitting.
Original message:

Create the Seciton -> Rel Section map when it is first needed. NFC.

Saves a walk over every section.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229536 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-17 20:31:13 +00:00
Tom Stellard
ec5b9ab433 R600/SI: Fix asam errors in SIFoldOperands
We were trying to fold into implicit uses, which led to out of bounds
access of the MCInstrDesc::OpInfo arrray.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229533 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-17 20:11:54 +00:00
Sanjay Patel
544843cee1 prevent folding a scalar FP load into a packed logical FP instruction (PR22371)
Change the memory operands in sse12_fp_packed_scalar_logical_alias from scalars to vectors. 
That's what the hardware packed logical FP instructions define: 128-bit memory operands.
There are no scalar versions of these instructions...because this is x86.

Generating the wrong code (folding a scalar load into a 128-bit load) is still possible
using the peephole optimization pass and the load folding tables. We won't completely
solve this bug until we either fix the lowering in fabs/fneg/fcopysign and any other
places where scalar FP logic is created or fix the load folding in foldMemoryOperandImpl()
to make sure it isn't changing the size of the load.

Differential Revision: http://reviews.llvm.org/D7474


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229531 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-17 20:08:21 +00:00
Rafael Espindola
38c028b361 Don't deference the section_end() iterator.
Hard to test given the undefined behavior nature.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229530 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-17 20:07:28 +00:00
Eric Christopher
24dded2342 Make the ARM AsmPrinter independent of global subtarget
initialization. Initialize the subtarget once per function and
migrate Emit{Start|End}OfAsmFile to either use attributes on the
TargetMachine or get information from the subtarget we'd use
for assembling. One bit (getISAEncoding) touched the general
AsmPrinter and the debug output. Handle this one by passing
the function for the subprogram down and updating all callers
and users.

The top-level-ness of the ARM attribute output for assembly is,
by nature, contrary to how we'd want to do this for an LTO
situation where we have multiple cpu architectures so this
solution is good enough for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229528 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-17 20:02:32 +00:00
Eric Christopher
cd3a8ad3e7 80-column fixups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229527 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-17 20:02:28 +00:00
Adrian Prantl
07d4ebdc92 DIBuilder: add trackIfUnresolved() to all nodes that may be cyclic.
Tested in clang/test/CodeGenObjCCXX/debug-info-cyclic.mm

rdar://problem/19839612

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229521 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-17 19:17:39 +00:00
Simon Atanasyan
602706ee58 [Object] Support reading 64-bit MIPS ELF archives
The 64-bit MIPS ELF archive file format is used by MIPS64 targets.
The main difference from a regular archive file is the symbol table format:
1. ar_name is equal to "/SYM64/"
2. number of symbols and offsets are 64-bit integers

http://techpubs.sgi.com/library/manuals/4000/007-4658-001/pdf/007-4658-001.pdf
Page 96

The patch allows reading of such archive files by llvm-nm, llvm-objdump
and other tools. But it does not support archive files with number of symbols
and/or offsets exceed 2^32. I think it is a rather rare case requires more
significant modification of `Archive` class code.

http://reviews.llvm.org/D7546

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229520 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-17 18:54:22 +00:00
Sanjay Patel
1115b2c27e Canonicalize splats as build_vectors (PR22283)
This is a follow-on patch to:
http://reviews.llvm.org/D7093

That patch canonicalized constant splats as build_vectors, 
and this patch removes the constant check so we can canonicalize
all splats as build_vectors.

This fixes the 2nd test case in PR22283:
http://llvm.org/bugs/show_bug.cgi?id=22283

The unfortunate code duplication between SelectionDAG and DAGCombiner
is discussed in the earlier patch review. At least this patch is just
removing code...

This improves an existing x86 AVX test and changes codegen in an ARM test.

Differential Revision: http://reviews.llvm.org/D7389


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229511 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-17 16:54:32 +00:00
Tom Stellard
7a7153e5ee R600/SI: Extend private extload pattern to include zext loads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229507 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-17 16:36:00 +00:00
Benjamin Kramer
1a50a12b43 Prefer SmallVector::append/insert over push_back loops.
Same functionality, but hoists the vector growth out of the loop.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229500 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-17 15:29:18 +00:00