Commit Graph

651 Commits

Author SHA1 Message Date
Rafael Espindola
9dcfdf61a8 CommentColumn is always 40. Simplify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199357 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 07:04:11 +00:00
Chandler Carruth
7f2eff792a [PM] Split DominatorTree into a concrete analysis result object which
can be used by both the new pass manager and the old.

This removes it from any of the virtual mess of the pass interfaces and
lets it derive cleanly from the DominatorTreeBase<> template. In turn,
tons of boilerplate interface can be nuked and it turns into a very
straightforward extension of the base DominatorTree interface.

The old analysis pass is now a simple wrapper. The names and style of
this split should match the split between CallGraph and
CallGraphWrapperPass. All of the users of DominatorTree have been
updated to match using many of the same tricks as with CallGraph. The
goal is that the common type remains the resulting DominatorTree rather
than the pass. This will make subsequent work toward the new pass
manager significantly easier.

Also in numerous places things became cleaner because I switched from
re-running the pass (!!! mid way through some other passes run!!!) to
directly recomputing the domtree.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199104 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 13:07:17 +00:00
Chandler Carruth
2073b0a63c [PM] Pull the generic graph algorithms and data structures for dominator
trees into the Support library.

These are all expressed in terms of the generic GraphTraits and CFG,
with no reliance on any concrete IR types. Putting them in support
clarifies that and makes the fact that the static analyzer in Clang uses
them much more sane. When moving the Dominators.h file into the IR
library I claimed that this was the right home for it but not something
I planned to work on. Oops.

So why am I doing this? It happens to be one step toward breaking the
requirement that IR verification can only be performed from inside of
a pass context, which completely blocks the implementation of
verification for the new pass manager infrastructure. Fixing it will
also allow removing the concept of the "preverify" step (WTF???) and
allow the verifier to cleanly flag functions which fail verification in
a way that precludes even computing dominance information. Currently,
that results in a fatal error even when you ask the verifier to not
fatally error. It's awesome like that.

The yak shaving will continue...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199095 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 10:52:56 +00:00
Chandler Carruth
56e1394c88 [cleanup] Move the Dominators.h and Verifier.h headers into the IR
directory. These passes are already defined in the IR library, and it
doesn't make any sense to have the headers in Analysis.

Long term, I think there is going to be a much better way to divide
these matters. The dominators code should be fully separated into the
abstract graph algorithm and have that put in Support where it becomes
obvious that evn Clang's CFGBlock's can use it. Then the verifier can
manually construct dominance information from the Support-driven
interface while the Analysis library can provide a pass which both
caches, reconstructs, and supports a nice update API.

But those are very long term, and so I don't want to leave the really
confusing structure until that day arrives.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199082 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 09:26:24 +00:00
Matt Arsenault
b9271b0ec5 Move declaration of variables down to first use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198794 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 21:47:14 +00:00
Chandler Carruth
974a445bd9 Re-sort all of the includes with ./utils/sort_includes.py so that
subsequent changes are easier to review. About to fix some layering
issues, and wanted to separate out the necessary churn.

Also comment and sink the include of "Windows.h" in three .inc files to
match the usage in Memory.inc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198685 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-07 11:48:04 +00:00
Andrew Trick
a38b0de893 Factor MI-Sched in preparation for post-ra scheduling support.
Factor the MachineFunctionPass into MachineSchedulerBase.

Split the DAG class into ScheduleDAGMI and SchedulerDAGMILive.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198119 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-28 21:56:47 +00:00
Tom Stellard
37ee312f77 R600: Allow ftrunc
v2: Add ftrunc->TRUNC pattern instead of replacing int_AMDGPU_trunc
v3: move ftrunc pattern next to TRUNC definition, it's available since R600

Patch By: Jan Vesely

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197783 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-20 05:11:55 +00:00
Rafael Espindola
b6601f1ce7 Small simplification, p0 is the same as p.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197699 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-19 16:51:03 +00:00
Matt Arsenault
e2c28ad84f R600/SI: Make private pointers be 32-bit.
Different sized address spaces should theoretically work
most of the time now, and since 64-bit add is currently
disabled, using more 32-bit pointers fixes some cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197659 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-19 05:32:55 +00:00
Andrew Trick
c4c5a1d526 Allow MachineCSE to coalesce trivial subregister copies the same way that it coalesces normal copies.
Without this, MachineCSE is powerless to handle redundant operations with truncated source operands.

This required fixing the 2-addr pass to handle tied subregisters. It isn't clear what combinations of subregisters can legally be tied, but the simple case of truncated source operands is now safely handled:

     %vreg11<def> = COPY %vreg1:sub_32bit; GR32:%vreg11 GR64:%vreg1
     %vreg12<def> = COPY %vreg2:sub_32bit; GR32:%vreg12 GR64:%vreg2
     %vreg13<def,tied1> = ADD32rr %vreg11<tied0>, %vreg12<kill>, %EFLAGS<imp-def>

Test case: cse-add-with-overflow.ll.

This exposed an existing bug in
PPCInstrInfo::commuteInstruction. Thanks to Rafael for the test case:
PowerPC/crash.ll.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197465 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-17 04:50:45 +00:00
Matt Arsenault
9bf2e090a0 Fix typo in instruction name.
SI_KIL -> SI_KILL

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197425 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-16 20:58:33 +00:00
Rafael Espindola
c4bc055bb4 One last cleanup of LLVM's DataLayout strings.
Produce them in the same order on every target. The order is that of
getStringRepresentation: e|E-i*-f*-v*-a*-s*-n*-S*.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197411 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-16 19:31:14 +00:00
Rafael Espindola
068fa852b6 Structure R600's computeDataLayout more like every other target.
While there, simplify "p3:32:32:32" to "p3:32:32".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197407 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-16 19:18:57 +00:00
Rafael Espindola
ea53c6ae30 The preferred alignment defaults to the abi alignment. Omit if it is the same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197400 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-16 18:01:51 +00:00
Rafael Espindola
63da3bbcf5 Don't duplicate the DataLayout defaults for integer, floats and vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197398 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-16 17:41:15 +00:00
Rafael Espindola
7ef5520e8c On DataLayout, omit the default of p:64:64:64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197397 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-16 17:15:29 +00:00
Matt Arsenault
729e476834 Don't manually calculate size in bytes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197327 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-14 18:21:59 +00:00
Rafael Espindola
ff0b475d92 Turn AMDGPUSubtarget::getDataLayout into a static function.
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197310 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-14 06:13:44 +00:00
Rafael Espindola
7dc7cc49a5 Don't set unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197064 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-11 20:40:57 +00:00
Tom Stellard
aa8dde50b7 R600: Re-format Processors.td
This makes it a little easier to read.

Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197058 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-11 17:51:51 +00:00
Tom Stellard
f8029c70e0 R600: Register AMDGPUCFGStructurizer pass
This enables -print-before-all to dump MachineInstrs after it is run.

Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197057 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-11 17:51:47 +00:00
Tom Stellard
23df2a7178 R600: Register R600EmitClauseMarkers pass
This enables -print-before-all to dump MachineInstrs after it is run.

Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197056 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-11 17:51:41 +00:00
NAKAMURA Takumi
0d87d72fa7 Prune redundant dependencies in LLVMBuild.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196988 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-11 00:30:57 +00:00
Matt Arsenault
17427fa9bb Use llvm_unreachable instead of assert(0)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196971 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-10 21:37:42 +00:00
Vincent Lejeune
a563c91840 R600: Fix an infinite loop when trying to reorganize export/tex vector input
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196923 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-10 14:43:31 +00:00
Vincent Lejeune
8ff689b443 R600: Fix input modifiers lost for Cayman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196922 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-10 14:43:27 +00:00
NAKAMURA Takumi
e1d55bb5d5 Add proper dependencies to LLVMBuild.txt in llvm/lib.
I'll prune redundant deps in LLVMBuild.txt, later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196881 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-10 05:39:34 +00:00
NAKAMURA Takumi
e0c0c4bdf6 Whitespaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196880 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-10 05:39:12 +00:00
Rafael Espindola
6bd88a58bb Don't set a variable to its default value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196807 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-09 19:36:11 +00:00
Vincent Lejeune
d254d3111e Add a RequireStructuredCFG Field to TargetMachine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196634 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-07 01:49:19 +00:00
Vincent Lejeune
7c8fbdac72 R600: Remove orphaned declarations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196633 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-07 01:49:10 +00:00
Eric Christopher
23b773836c Fix an index array check.
Patch by Marius Wachtler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196561 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-06 02:45:24 +00:00
Rafael Espindola
6b11950e39 Add a default constructor to get deterministic behavior.
Should fix the msan and valgrind bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196509 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-05 16:21:17 +00:00
Alp Toker
087ab613f4 Correct word hyphenations
This patch tries to avoid unrelated changes other than fixing a few
hyphen-related ambiguities and contractions in nearby lines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196471 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-05 05:44:44 +00:00
Matt Arsenault
87234703e8 R600/SI: Add comments for number of used registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196467 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-05 05:15:35 +00:00
Rafael Espindola
387d4ea375 Don't set PrivateGlobalPrefix for NVPTX and R600.
These targets have special asm printers that don't use these.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196187 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-03 01:03:35 +00:00
Rafael Espindola
29a0d2abfe Convert two char* that are only ever used as booleans to bool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196168 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-02 23:04:51 +00:00
Vincent Lejeune
7043c7a35e R600: Workaround for cayman loop bug
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196121 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-02 17:29:37 +00:00
Rafael Espindola
4a6855441c Change the default of AsmWriterClassName and isMCAsmWriter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196065 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-02 04:55:42 +00:00
NAKAMURA Takumi
ef70d2a393 [CMake] Let add_public_tablegen_target() provide intrinsics_gen, too.
I think, in principle, intrinsics_gen may be added explicitly.
That said, it can be added incidentally, since each target already has dependencies to llvm-tblgen.
Almost all source files depend on both CommonTaleGen and intrinsics_gen.

Explicit add_dependencies() have been pruned under lib/Target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195929 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-28 17:04:31 +00:00
NAKAMURA Takumi
ad363187c4 [CMake] Let add_public_tablegen_target responsible to provide dependency to CommonTableGen.
add_public_tablegen_target adds *CommonTableGen to LLVM_COMMON_DEPENDS.
LLVM_COMMON_DEPENDS affects add_llvm_library (and other add_target stuff) within its scope.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195927 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-28 17:04:04 +00:00
NAKAMURA Takumi
98bb341955 [CMake] Prune include_directories() in llvm/lib/Target, take #2.
I forgot to commit them. They were staging in my local repo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195924 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-28 15:30:37 +00:00
Rafael Espindola
98fef8e6c0 The R600 has its own asm printer which doesn't use GlobalPrefix. Drop it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195883 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-27 21:52:37 +00:00
Tom Stellard
8a6b7df6f8 R600: Expand vector FABS
NOTE: This is a candidate for the 3.4 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195881 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-27 21:23:39 +00:00
Tom Stellard
aa6ec15caf R600/SI: Implement spilling of SGPRs v5
SGPRs are spilled into VGPRs using the {READ,WRITE}LANE_B32 instructions.

v2:
  - Fix encoding of Lane Mask
  - Use correct register flags, so we don't overwrite the low dword
    when restoring multi-dword registers.

v3:
  - Register spilling seems to hang the GPU, so replace all shaders
    that need spilling with a dummy shader.

v4:
  - Fix *LANE definitions
  - Change destination reg class for 32-bit SMRD instructions

v5:
  - Remove small optimization that was crashing Serious Sam 3.

https://bugs.freedesktop.org/show_bug.cgi?id=68224
https://bugs.freedesktop.org/show_bug.cgi?id=71285

NOTE: This is a candidate for the 3.4 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195880 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-27 21:23:35 +00:00
Tom Stellard
0cbf943733 R600/SI: Use SGPR_32 register class for 32-bit SMRD outputs
Writing to the M0 register from an SMRD instruction hangs the GPU, so
we need to use the SGPR_32 register class, which does not include M0.

NOTE: This is a candidate for the 3.4 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195879 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-27 21:23:29 +00:00
Tom Stellard
496dbfe7b9 R600: Add support for ISD::FROUND
NOTE: This is a candidate for the 3.4 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195878 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-27 21:23:20 +00:00
Tom Stellard
0f39827340 R600/SI: Fixing handling of condition codes
We were ignoring the ordered/onordered bits and also the signed/unsigned
bits of condition codes when lowering the DAG to MachineInstrs.

NOTE: This is a candidate for the 3.4 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195514 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-22 23:07:58 +00:00
Tom Stellard
8d56c59235 R600: Implement TargetInstrInfo::isLegalToSplitMBBAt()
Splitting a basic block will create a new ALU clause, so we need to make
sure we aren't moving uses of registers that are local to their
current clause into a new one.

I had a test case for this, but unfortunately unrelated schedule changes
invalidated it, and I wasn't been able to come up with another one.

NOTE: This is a candidate for the 3.4 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195399 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-22 00:41:08 +00:00