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4dd9b091cc
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5273 Commits

Author SHA1 Message Date
Bill Wendling
4dd9b091cc Support creating a constant pool value for a machine basic block. 
This is used when we want to take the address of a machine basic block, but it's
not associated with a BB in LLVM IR.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140823 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-29 23:48:44 +00:00
NAKAMURA Takumi
13f4a6c940 Target/ARM: Unbreak! CMake! Build! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140774 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-29 03:32:49 +00:00
Jakob Stoklund Olesen
adcb634d85 Delete NEONMoveFix, now unused. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140773 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-29 02:56:45 +00:00
Jakob Stoklund Olesen
8bb3d3cb30 Use ExecutionDepsFix instead of NEONMoveFix. 
This enables NEON domain tracking across basic blocks, but should
otherwise do the same thing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140772 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-29 02:48:41 +00:00
Bill Wendling
3511cedf36 Move to ISelLowering. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140754 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-29 01:13:55 +00:00
Evan Cheng
9b88d2d782 Tighten a ARM dag combine condition to avoid an identity transformation, which 
ends up introducing a cycle in the DAG.

rdar://10196296


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140733 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-28 23:16:31 +00:00
Bill Wendling
b18abd077e Perform the lowering only if there are invokes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140719 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-28 20:29:45 +00:00
Bill Wendling
39689c8154 Ahem...actually *add* the ARMSjLjLowering pass to the pass manager. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140718 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-28 20:29:28 +00:00
James Molloy
acad68da50 Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. 
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.

Add decoder and disassembler tests.

Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-28 14:21:38 +00:00
Ted Kremenek
833217bfb9 Unbreak CMake build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140655 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-27 23:29:59 +00:00
Jakob Stoklund Olesen
13fd601e0f Implement TII::get/setExecutionDomain() for ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140653 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-27 22:57:21 +00:00
Jim Grosbach
25ddc2bf7e ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w. 
Add inst alias to handle these assembly forms. Add tests, too.

rdar://10178799


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140647 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-27 22:18:54 +00:00
Bill Wendling
0481d29d49 This is the start of the new SjLj EH preparation pass, which will replace the 
current IR-level pass.

The old SjLj EH pass has some problems, especially with the new EH model. Most
significantly, it violates some of the new restrictions the new model has. For
instance, the 'dispatch' table wants to jump to the landing pad, but we cannot
allow that because only an invoke's unwind edge can jump to a landing pad. This
requires us to mangle the code something awful. In addition, we need to keep the
now dead landingpad instructions around instead of CSE'ing them because the
DWARF emitter uses that information (they are dead because no control flow edge
will execute them - the control flow edge from an invoke's unwind is superceded
by the edge coming from the dispatch).

Basically, this pass belongs not at the IR level where SSA is king, but at the
code-gen level, where we have more flexibility.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140646 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-27 22:14:12 +00:00
Jim Grosbach
5405d58e21 Rename AddSelectionDAGCSEId() to addSelectionDAGCSEId(). 
Naming conventions consistency. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140636 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-27 20:59:33 +00:00
Jakob Stoklund Olesen
8e695eb5fa Use existing function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140615 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-27 17:55:08 +00:00
Owen Anderson
2dafe200ca Remove extraneous commit garbage. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140581 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 23:14:02 +00:00
Owen Anderson
0afa0094af ASR #32 is not allowed on Thumb2 USAT and SSAT instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140560 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 21:06:22 +00:00
David Meyer
8f418b11d2 PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL 2011-06-09-TailCallByVal and 2010-11-04-BigByval 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140516 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 06:13:20 +00:00
Owen Anderson
4d2a00147d Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset of #-0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140426 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 22:25:02 +00:00
Jakob Stoklund Olesen
11ebe3d7c1 Also match negative offsets for addrmode3 and addrmode5. 
Math is hard, and isScaledConstantInRange() always returned false for
negative constants.  It was doing unsigned division of negative numbers
before casting back to signed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140425 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 22:10:33 +00:00
Owen Anderson
4a713570b6 Add more fixed bits to USAT16 encoding to filter out incorrect decodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140422 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 21:57:50 +00:00
Owen Anderson
0781c1f700 Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140420 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 21:26:40 +00:00
Owen Anderson
31d485ec9a Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140415 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 21:07:25 +00:00
Owen Anderson
df0caeb6ec Revert r140412. This affects more instructions than intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140413 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 21:02:01 +00:00
Owen Anderson
d256056581 Thumb2 register-shifted-register loads cannot target the PC or the SP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140412 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 21:00:32 +00:00
Owen Anderson
6126870193 Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix other test failures I caused. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140284 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 23:53:44 +00:00
Owen Anderson
e136872970 Print out immediate offset versions of PC-relative load/store instructions as [pc, #123] rather than simply #123. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140283 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 23:44:46 +00:00
Owen Anderson
519020adf1 These do not need to be conditional on the presence of CommentStream, as they have a fallback path now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140267 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 17:58:45 +00:00
Andrew Trick
3be654f808 Lower ARM adds/subs to add/sub after adding optional CPSR operand. 
This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140228 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 02:20:46 +00:00
Andrew Trick
e23dc9c0ef whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140227 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 02:17:37 +00:00
Owen Anderson
317eaf1993 In the disassembler C API, be careful not to confuse the comment streamer that the disassembler outputs annotations on with the streamer that the InstPrinter will print them on. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140217 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 00:25:23 +00:00
Evan Cheng
0d18174f0f Fix a bug introduced during refactoring a couple of months ago. Cortex-M3 does not support Thumb2 dsp instructions. rdar://10152911. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140181 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 21:38:18 +00:00
Andrew Trick
83a8031336 Restore hasPostISelHook tblgen flag. 
No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140160 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 18:22:31 +00:00
Andrew Trick
4815d56bb2 ARM isel bug fix for adds/subs operands. 
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140134 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 03:17:40 +00:00
Andrew Trick
3af7a67629 whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140133 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 03:06:13 +00:00
Jim Grosbach
50f1c37123 Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140125 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 00:46:54 +00:00
Jim Grosbach
6053cd956f Thumb2 assembly parsing and encoding for USAX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140119 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 00:30:45 +00:00
Jim Grosbach
8c9898454c Remove incorrect comments. These are not disassmebly only patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140116 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 00:26:34 +00:00
Jim Grosbach
ab3bf97fe0 Thumb2 assembly parsing and encoding for UQASX/UQSAX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140111 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 00:18:52 +00:00
Jim Grosbach
abb8aacef2 Thumb1 convenience aliases for disassembler round-trip testing. CPS instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140108 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 00:10:37 +00:00
Jim Grosbach
26215425da Thumb CPS definition is not disassembler only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140106 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 00:00:06 +00:00
Jim Grosbach
0efe213ed5 Thumb2 range check on CPS mode immediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140105 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:58:31 +00:00
Owen Anderson
d9346fbb06 tMOVSr is not allowed in an IT block either. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140104 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:57:20 +00:00
Owen Anderson
9f666b5f2e CPS instructions are UNPREDICTABLE inside IT blocks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140102 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:47:10 +00:00
Jim Grosbach
32f36899e9 Tidy up comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140099 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:38:34 +00:00
Jim Grosbach
d5d0e81a4b Thumb2 assembly parsing and encoding for UMAAL/UMLAL/UMULL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140095 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:31:02 +00:00
Jim Grosbach
6729c48b94 Thumb2 assembly parsing and encoding for UHASX/UHSAX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140088 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:13:25 +00:00
Jim Grosbach
4032eaf98c Thumb2 assembly parsing and encoding for UASX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140085 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:05:22 +00:00
Owen Anderson
04c7877894 Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not in the middle. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140079 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 22:34:23 +00:00
Jim Grosbach
7f739bee26 Thumb2 assembly parsing and encoding for TBB/TBH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140078 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 22:21:13 +00:00