Commit Graph

4460 Commits

Author SHA1 Message Date
Bill Wendling
4f02c41a36 Expand test to make sure that we can generate compact unwind from an ASM file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190347 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-09 20:10:54 +00:00
Bill Wendling
c3cee57f7d Generate compact unwind encoding from CFI directives.
We used to generate the compact unwind encoding from the machine
instructions. However, this had the problem that if the user used `-save-temps'
or compiled their hand-written `.s' file (with CFI directives), we wouldn't
generate the compact unwind encoding.

Move the algorithm that generates the compact unwind encoding into the
MCAsmBackend. This way we can generate the encoding whether the code is from a
`.ll' or `.s' file.

<rdar://problem/13623355>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190290 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-09 02:37:14 +00:00
Manman Ren
1307103dff Debug Info Testing: updated to use NULL instead of "i32 0" in a few fields.
Field 2 of DIType (Context), field 9 of DIDerivedType (TypeDerivedFrom),
field 12 of DICompositeType (ContainingType), fields 2, 7, 12 of DISubprogram
(Context, Type, ContainingType).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190205 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 21:03:58 +00:00
Tim Northover
a5eeb9da05 SelectionDAG: create correct BooleanContent constants
Occasionally DAGCombiner can spot that a SETCC operation is completely
redundant and reduce it to "all true" or "all false". If this happens to a
vector, the value produced has to take account of what a normal comparison
would have produced, which may be an all-1s bitmask.

The fix in SelectionDAG.cpp is tested, however, as far as I can see the code in
TargetLowering.cpp is possibly unreachable and almost certainly irrelevant when
triggered so there are no tests. However, I believe it's still clearly the
right change and may save someone else some hassle if it suddenly becomes
reachable. So I'm doing it anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190147 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 12:38:12 +00:00
Juergen Ributzka
d7174719a9 [X86] Perform VSELECT DAG combines also before DAG type legalization.
If the DAG already has only legal types, then the second round of DAG combines
is skipped. In this case VSELECT+SETCC patterns that match a more efficient
instruction (e.g. min/max) are never recognized.

This fix allows VSELECT+SETCC combines if the types are already legal before DAG
type legalization.

Reviewer: Nadav

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190105 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-05 23:02:56 +00:00
Andrew Trick
d4486ebd5f mi-sched: Force bottom up scheduling for generic targets.
Fast register pressure tracking currently only takes effect during
bottom up scheduling. Forcing this is a bit faster and simpler for
targets that don't have many scheduling constraints and don't need
top-down scheduling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190014 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-04 23:54:00 +00:00
NAKAMURA Takumi
4629e0da6a FileCheck-ize three tests of llvm/test/CodeGen/X86/h-register(s).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189755 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-02 12:00:53 +00:00
NAKAMURA Takumi
b9edd20706 llvm/test/CodeGen/X86: Update tests with -mattr=-bmi not to take BMI, corresponding to Craig's r189742.
AMD Piledriver builder detected failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189754 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-02 12:00:46 +00:00
Craig Topper
69c474ffa8 Create BEXTR instructions for (and ((sra or srl) x, imm), (2**size - 1)). Fixes PR17028.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189742 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-02 07:53:17 +00:00
Elena Demikhovsky
cafcc99857 AVX-512: gather-scatter tests; added foldable instructions;
Specify GATHER/SCATTER as heavy instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189736 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-02 07:12:29 +00:00
Elena Demikhovsky
6adcd58d3c AVX-512: Added GATHER and SCATTER instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189729 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-01 14:24:41 +00:00
Craig Topper
b6ac30a155 Teach X86 backend to create BMI2 BZHI instructions from (and X, (add (shl 1, Y), -1)). Fixes PR17038.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189653 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-30 06:52:21 +00:00
Andrew Trick
da6fc15f0f mi-sched: improve the generic register pressure comparison.
Only compare pressure within the same set. When multiple sets are
affected, we prioritize the most constrained set.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189641 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-30 04:27:29 +00:00
Andrew Trick
4c60b8a78d mi-sched: Precompute a PressureDiff for each instruction, adjust for liveness later.
Created SUPressureDiffs array to hold the per node PDiff computed during DAG building.

Added a getUpwardPressureDelta API that will soon replace the old
one. Compute PressureDelta here from the precomputed PressureDiffs.

Updating for liveness will come next.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189640 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-30 03:49:48 +00:00
Elena Demikhovsky
4edfa2278a AVX-512: added extend and truncate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189580 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-29 11:56:53 +00:00
Elena Demikhovsky
2fb982aa72 AVX-512: added SQRT, VRSQRT14, VCOMISS, VUCOMISS, VRCP14, VPABS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189472 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-28 11:21:58 +00:00
Eric Christopher
6e74bfc0e6 Move some debug testcases to the debug info directory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189418 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-27 23:48:57 +00:00
Elena Demikhovsky
d371d4f0f4 AVX-512: added conversion instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189349 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-27 13:54:04 +00:00
Tim Northover
5d8c2e460c DAGCombiner: make sure or/shl/srl really has zero high bits before forming bswap
We want to convert code like (or (srl N, 8), (shl N, 8)) into (srl (bswap N),
const), but this is only valid if the bits above 16 on the source pattern are
0, the checks we were doing on this were slightly wrong before.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189348 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-27 13:46:45 +00:00
Elena Demikhovsky
1567abe74f AVX-512: Added FMA instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189326 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-27 08:39:25 +00:00
Manman Ren
6e3cd0ebe2 Debug Info: add an identifier field to DICompositeType.
DICompositeType will have an identifier field at position 14. For now, the
field is set to null in DIBuilder.
For DICompositeTypes where the template argument field (the 13th field)
was optional, modify DIBuilder to make sure the template argument field is set.
Now DICompositeType has 15 fields.

Update DIBuilder to use NULL instead of "i32 0" for null value of a MDNode.
Update verifier to check that DICompositeType has 15 fields and the last
field is null or a MDString.

Update testing cases to include an extra field for DICompositeType.
The identifier field will be used by type uniquing so a front end can
genearte a DICompositeType with a unique identifer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189282 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 22:39:55 +00:00
Elena Demikhovsky
92bfb54770 AVX-512: Added shuffle instructions -
VPSHUFD, VPERMILPS, VMOVDDUP, VMOVLHPS, VMOVHLPS, VSHUFPS, VALIGN
 single and double forms.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189215 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 12:45:35 +00:00
Elena Demikhovsky
41f7baf181 AVX-512: added UNPACK instructions and tests for all-zero/all-ones vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189189 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-25 12:54:30 +00:00
Rafael Espindola
cb1339ebeb Update test to use rdrnd instead of rdrand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189146 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 20:49:02 +00:00
Rafael Espindola
9b14371830 Update tests to use sse4.2 instead of sse42.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189145 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 20:46:35 +00:00
Rafael Espindola
7cb1b5f5bf Replace more uses of sse41 with sse4.1.
llc using the host cpu features and *waning* on unknown features is probably
not a good thing :-(

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189144 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 20:39:19 +00:00
Rafael Espindola
56afd5e90b Update a test that I missed in the previous commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189143 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 20:27:02 +00:00
Rafael Espindola
4aa8bdaa46 Rename features to match what gcc and clang use.
There is no advantage in being different and using the same names simplifies
clang a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189141 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 20:21:34 +00:00
Bill Wendling
80075c482c Update to remove the no-frame-pointer-elim-non-leaf flag if it was set to 'false'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189068 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-22 21:28:54 +00:00
Bill Wendling
cec45be796 Fix some tests. The 'false' version just omits the attribute altogether.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189065 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-22 21:20:14 +00:00
Manman Ren
094637408b [Debug Info Tests] Update testing cases.
A single metadata will not span multiple lines. This also helps me with
my script to automatic update the testing cases.
A debug info testing case should have a llvm.dbg.cu.
Do not use hard-coded id for debug nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189033 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-22 17:11:18 +00:00
Michael Gottesman
021f3280fe [stackprotector] When finding the split point to splice off the end of a parentmbb into a successmbb, include any DBG_VALUE MI.
Fix for PR16954.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188987 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-22 05:40:50 +00:00
Manman Ren
bf9d6e5c37 TBAA: remove !tbaa from testing cases when they are not needed.
This will make it easier to turn on struct-path aware TBAA since the metadata
format will change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188944 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-21 22:20:53 +00:00
Juergen Ributzka
915e936de2 Teach BaseIndexOffset::match to identify base pointers in loops.
The small utility function that pattern matches Base + Index +
Offset patterns for loads and stores fails to recognize the base
pointer for loads/stores from/into an array at offset 0 inside a
loop. As a result DAGCombiner::MergeConsecutiveStores was not able
to merge all stores.

This commit fixes the issue by adding an additional pattern match
and also a test case.

Reviewer: Nadav

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188936 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-21 21:53:38 +00:00
Joey Gouly
159b6f1775 Add -mcpu to two X86 tests.
These tests are failing on Haswell CPUs due to different instruction selection.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188908 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-21 17:14:31 +00:00
Elena Demikhovsky
8ba76daba0 AVX-512: Added SHIFT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188899 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-21 09:36:02 +00:00
Elena Demikhovsky
38cd21a3e9 AVX-512: Added more patterns for VMOVSS, VMOVSD, VMOVD, VMOVQ
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188786 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 11:00:29 +00:00
Paul Redmond
d345395ec9 Improve the widening of integral binary vector operations
- split WidenVecRes_Binary into WidenVecRes_Binary and WidenVecRes_BinaryCanTrap
  - WidenVecRes_BinaryCanTrap preserves the original behaviour for operations
    that can trap
  - WidenVecRes_Binary simply widens the operation and improves codegen for
    3-element vectors by allowing widening and promotion on x86 (matches the
    behaviour of unary and ternary operation widening)
- use WidenVecRes_Binary for operations on integers.

Reviewed by: nrotem



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188699 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-19 20:01:35 +00:00
Elena Demikhovsky
f12df0ad50 AVX-512: added arithmetic and logical operations.
ADD, SUB, MUL integer and FP types. OR, AND, XOR.
Added embeded broadcast form for these instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188673 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-19 13:26:14 +00:00
Elena Demikhovsky
3491d67d3a AVX-512: Added VMOVD, VMOVQ, VMOVSS, VMOVSD instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188637 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-18 13:08:57 +00:00
Daniel Dunbar
07d4e2813c [tests] Another attempt to workaround broken misched-copy.s test on some buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188567 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-16 18:01:18 +00:00
Craig Topper
0163356ad1 Don't use v16i32 for load pattern matching. All 512-bit loads are cated to v8i64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188534 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-16 06:07:34 +00:00
Daniel Dunbar
32b34f7f72 [tests] Add a hack to eliminate some dangling .s files on buildbots.
- Benjamin fixed the emission of this file in r179937, but it still lives on a
   few buildbots. We should probably clean up the build dirs once in a while,
   eh?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188527 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-16 02:54:00 +00:00
Daniel Dunbar
24ec2e5a72 [tests] Cleanup initialization of test suffixes.
- Instead of setting the suffixes in a bunch of places, just set one master
   list in the top-level config. We now only modify the suffix list in a few
   suites that have one particular unique suffix (.ml, .mc, .yaml, .td, .py).

 - Aside from removing the need for a bunch of lit.local.cfg files, this enables
   4 tests that were inadvertently being skipped (one in
   Transforms/BranchFolding, a .s file each in DebugInfo/AArch64 and
   CodeGen/PowerPC, and one in CodeGen/SI which is now failing and has been
   XFAILED).

 - This commit also fixes a bunch of config files to use config.root instead of
   older copy-pasted code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188513 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-16 00:37:11 +00:00
Craig Topper
d36e1efa4b Revert r188449 as it turns out we're just missing the instructions that need the v16i32/v16f32 matching.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188454 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-15 08:38:25 +00:00
Craig Topper
46ceaf4ba6 Don't let isPermImmMask handle v16i32 since VPERMI doesn't match on that type. Remove 128-bit vector handling from isPermImmMask too, it's covered by isPSHUFDMask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188449 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-15 07:30:51 +00:00
NAKAMURA Takumi
7cd85b7492 llvm/test/CodeGen/X86/setcc-sentinals.ll: Relax expressions for x86_64-win32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188340 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-14 00:46:00 +00:00
Jim Grosbach
51a0280d29 DAG: Combine (and (setne X, 0), (setne X, -1)) -> (setuge (add X, 1), 2)
A common idiom is to use zero and all-ones as sentinal values and to
check for both in a single conditional ("x != 0 && x != (unsigned)-1").
That generates code, for i32, like:
  testl %edi, %edi
  setne %al
  cmpl  $-1, %edi
  setne %cl
  andb  %al, %cl

With this transform, we generate the simpler:
  incl  %edi
  cmpl  $1, %edi
  seta  %al

Similar improvements for other integer sizes and on other platforms. In
general, combining the two setcc instructions into one is better.

rdar://14689217

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188315 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-13 21:30:58 +00:00
Elena Demikhovsky
4d36bd80e6 AVX-512: Added CMP and BLEND instructions.
Lowering for SETCC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188265 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-13 13:24:07 +00:00
Tim Northover
dcef6a7400 Fix FileCheck --check-prefix lines.
Various tests had sprung up over the years which had --check-prefix=ABC on the
RUN line, but "CHECK-ABC:" later on. This happened to work before, but was
strictly incorrect. FileCheck is getting stricter soon though.

Patch by Ron Ofir.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188173 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-12 12:43:26 +00:00