tests:
Running /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.HEAD.src/test/Verifier/dg.exp ...
FAIL: /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.HEAD.src/test/Verifier/gcread-ptrptr.ll for PR1633
Failed with exit(1) at line 1
while running: not llvm-as < /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.HEAD.src/test/Verifier/gcread-ptrptr.ll >& /dev/null
child process exited abnormally
FAIL: /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.HEAD.src/test/Verifier/gcroot-alloca.ll for PR1633
Failed with exit(1) at line 1
while running: not llvm-as < /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.HEAD.src/test/Verifier/gcroot-alloca.ll >& /dev/null
child process exited abnormally
FAIL: /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.HEAD.src/test/Verifier/gcroot-meta.ll for PR1633
Failed with exit(1) at line 1
while running: not llvm-as < /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.HEAD.src/test/Verifier/gcroot-meta.ll >& /dev/null
child process exited abnormally
FAIL: ndbox/Buildbot/llvm/full-llvm/build/llvm.HEAD.src/test/Verifier/gcroot-ptrptr.ll for PR1633
Failed with exit(1) at line 1
while running: not llvm-as < /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.HEAD.src/test/Verifier/gcroot-ptrptr.ll >& /dev/null
child process exited abnormally
FAIL: /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.HEAD.src/test/Verifier/gcwrite-ptrptr.ll for PR1633
Failed with exit(1) at line 1
while running: not llvm-as < /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.HEAD.src/test/Verifier/gcwrite-ptrptr.ll >& /dev/null
child process exited abnormally
=== Summary ===
# of expected passes 3021
# of unexpected failures 6
# of expected failures 16
make[1]: *** [check-local] Error 1
make: *** [check] Error 2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55233 91177308-0d34-0410-b5e6-96231b3b80d8
process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.
Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.
To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55219 91177308-0d34-0410-b5e6-96231b3b80d8
instructions that define the full 32 or 64-bit value. When anyexting
from i8 to i16 or i32, it's not necessary to zero out the high
portion of the register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55190 91177308-0d34-0410-b5e6-96231b3b80d8
handled correctly, and change a few SmallVector uses to use
size 0 to more clearly reflect their intent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55181 91177308-0d34-0410-b5e6-96231b3b80d8
so that lwarx and stwcx are always executed the same number of times.
This is important for performance, I'm told.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55163 91177308-0d34-0410-b5e6-96231b3b80d8
and use it in FastISelEmitter.cpp, and make FastISel
subtarget aware. Among other things, this lets it work
properly on x86 targets that don't have SSE, where it
successfully selects x87 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55156 91177308-0d34-0410-b5e6-96231b3b80d8
1. x86-64 byval alignment should be max of 8 and alignment of type. Previously the code was not doing what the commit message was saying.
2. Do not use byte repeat move and store operations. These are slow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55139 91177308-0d34-0410-b5e6-96231b3b80d8
