6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-21 00:32:23 +00:00
Code Issues Projects Releases Wiki Activity
73,858 Commits 39 Branches 0 Tags 277 MiB
53c95880f0
Commit Graph

73858 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Bruno Cardoso Lopes
53c95880f0 We already support 256-bit packed ADD, SUB, DIV, MUL. Add testcases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135099 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 22:28:55 +00:00
Jim Grosbach
14ab1c3387 ARM parsing and encoding tests for CMN/CMP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135098 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 22:26:58 +00:00
David Greene
afd54269ab struct Init -> class Init 
Rename struct Init to class Init for consistency and in preparation
for making Init a FoldingSetNode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135097 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 22:25:51 +00:00
Jakob Stoklund Olesen
54c74e906a Revert r135074 and r135080. They broke clamscan. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135096 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 22:20:09 +00:00
Jim Grosbach
d986bc66bc Shuffle ARM assembly tests a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135095 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 22:19:10 +00:00
Jim Grosbach
1cbb0c16a1 Revert 135093. Think-o. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135094 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 22:06:11 +00:00
Jim Grosbach
91eb0aa5de Correct range for thumb co-processor immediate 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135093 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 22:03:11 +00:00
Jim Grosbach
83ab070fc1 Range checking for CDP[2] immediates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135092 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 22:01:08 +00:00
Bruno Cardoso Lopes
466b022c99 Make X86ISD::ANDNP more general and Codegen 256-bit VANDNP. A more 
general version of X86ISD::ANDNP also opened the room for a little bit
of refactoring.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135088 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 21:36:51 +00:00
Bruno Cardoso Lopes
c1af4772f1 The target specific node PANDN name is misleading. That happens because 
it's later selected to a ANDNPD/ANDNPS instruction instead of the PANDN
instruction. Rename it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135087 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 21:36:47 +00:00
Jim Grosbach
e35c5e06fe Cleanup Thumb co-processor instructions a bit. 
Combine redundant base classes and such. No indended functional change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135085 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 21:35:10 +00:00
Eli Friedman
2a01946de4 Make sure we don't combine a large displacement and a frame index in the same addressing mode on x86-64. It can overflow, leading to a crash/miscompile. 
<rdar://problem/9763308>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135084 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 21:29:53 +00:00
Jim Grosbach
0d8dae292a Parameterize away the ARM T1Cop class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135082 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 21:17:59 +00:00
Jim Grosbach
9bb098ad3a Fix predicates for Thumb co-processor instructions. 
They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135081 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 21:14:23 +00:00
Jakob Stoklund Olesen
3bae1bf62e Only keep the global split candidates that work out. 
Some pysical registers create split solutions that would spill anywhere.
They should not even be considered in future multi-way global splits.

This does not affect code generation (yet).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135080 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 20:49:46 +00:00
Eli Friedman
4977eb5eb5 Refactor out checking for displacements on x86-64 addressing modes. No functionality change. Refactoring in preparation for an additional safety check in FoldOffsetIntoAddress. 
Part of <rdar://problem/9763308>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135079 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 20:44:23 +00:00
Jim Grosbach
f333d471d2 Testcases for ARM assembly BX/BXJ instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135078 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 20:25:46 +00:00
Jim Grosbach
898e7e26a5 Fix encoding for ARM BXJ instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135077 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 20:25:01 +00:00
Jim Grosbach
d447ac6c8c Fix encoding of predicate bits on ARM BX_pred. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135076 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 20:21:31 +00:00
Jakob Stoklund Olesen
1337e2b75a Move the InterferenceCache cursor into the GlobalSplitCand struct. 
This is in preparation of supporting multiple global split candidates in
a single live range split operation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135074 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 20:14:52 +00:00
Jim Grosbach
37023b05c8 Testcases for ARM assembly BLX/BL instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135072 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 20:11:04 +00:00
Jim Grosbach
fff76ee7ef Range checking for 16-bit immediates in ARM assembly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135071 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 20:10:10 +00:00
Jay Foad
d1863560cb Revert r135042. As Chris pointed out, it had no effect, and was based on 
a complete misunderstanding of the code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135070 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 20:05:31 +00:00
Evan Cheng
9bc402c8d4 Fix up TargetLoweringObjectFile ctors to properly initialize fields. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135068 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 19:54:59 +00:00
Jim Grosbach
619e0d6d95 Give the ARM BKPT instruction the right operand type. 
The immediate is of limited range and the operand type should reflect that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135066 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 19:24:09 +00:00
Evan Cheng
3fd6e755d0 Change test case, one that actually failed before my commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135064 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 19:19:44 +00:00
Jim Grosbach
21101d60ce Add tests for ARM parsing of 'BKPT' instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135063 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 19:17:36 +00:00
Jim Grosbach
76cbe02cdd Fix copy-pasto. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135062 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 19:16:30 +00:00
Jim Grosbach
e52240c370 Add tests for ARM parsing of 'BIC' instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135061 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 19:12:32 +00:00
Jim Grosbach
7ed6d22e96 Add some FIXMEs. 
Keeping the instructions in alphabetical order, just like in the ARM ARM.
Adding FIXMEs for skipped instructions when adding tests out of order.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135060 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 19:10:23 +00:00
Evan Cheng
c4d858d4fd Revert accidental commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135059 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 19:09:08 +00:00
Evan Cheng
93a635c82c It's not safe to fold (fptrunc (sqrt (fpext x))) to (sqrtf x) if there is another use of sqrt. rdar://9763193 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135058 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 19:08:16 +00:00
Jim Grosbach
59642c2600 Add tests for ARM parsing of 'AND' instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135056 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 18:55:14 +00:00
Jim Grosbach
19906729a4 Improve ARM assembly parsing diagnostics a bit. 
Catch potential cascading errors on a malformed so_reg operand and bail after
the first error.

Add some tests for the diagnostics we do want.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135055 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 18:49:30 +00:00
Jim Grosbach
da9f278c74 Add tests for ARM parsing of 'ADD' instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135053 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 18:12:46 +00:00
Jim Grosbach
37ee464ea9 Destination register operand is optional for ADC and SBC ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135052 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 17:57:17 +00:00
Jim Grosbach
e8606dc7c8 Flesh out ARM Parser support for shifted-register operands. 
Now works for parsing register shifted register and register shifted
immediate arithmetic instructions, including the 'rrx' rotate with extend.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135049 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 17:50:29 +00:00
Jim Grosbach
aa4cc1a6d7 80 columns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135047 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 17:25:55 +00:00
Jim Grosbach
b7f689bab9 Update MCParsedAsmOperand debug methods. 
Update the debug output interface for MCParsedAsmOperand to have a print()
method which takes an output stream argument, an << operator which invokes
the print method using the given stream, and a dump() method which prints
the operand to the dbgs() stream. This makes the interface more consistent
with the rest of LLVM, and more convenient to use at the debugger command
line.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135043 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 15:34:57 +00:00
Jay Foad
75f67e0d8d Really cache function types and anonymous struct types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135042 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 10:39:49 +00:00
Jay Foad
fc6d3a4986 Convert InsertValueInst and ExtractValueInst APIs to use ArrayRef. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135040 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 10:26:04 +00:00
Jay Foad
5d4f9909c4 Add some bits that I found useful when converting InsertValueInst and 
ExtractValueInst APIs to use ArrayRef: a new constructor taking a
(begin, end) range, and operators == and != for element-wise comparison.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135039 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 09:15:05 +00:00
Danil Malyshev
cf852dc49b Add to RuntimeDyld support different object formats 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135037 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 07:57:58 +00:00
Chris Lattner
c09ef37171 stop leaking all named struct types with an empty name. Thanks 
to Benjamin Kramer for steering me in the right direction here.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135031 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 04:22:39 +00:00
Evan Cheng
3b737081e4 Add an entry. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135024 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 01:33:00 +00:00
Bruno Cardoso Lopes
61905f0139 AVX Codegen support for 256-bit versions of vandps, vandpd, vorps, vorpd, vxorps, vxorpd 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135023 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 01:15:33 +00:00
Bill Wendling
8440fe2166 Don't emit the FDE end label if the last thing emitted was a compact unwind and 
not the FDE


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135020 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 00:49:09 +00:00
Eli Friedman
5cf2ee1f80 Add an assert (which should never trigger) that triggers on a testcase I'm looking at. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135018 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 00:44:29 +00:00
Evan Cheng
e721f5c8d3 Improve codegen for select's: 
if (x != 0) x = 1
if (x == 1) x = 1

Previous codegen looks like this:
        mov     r1, r0
        cmp     r1, #1
        mov     r0, #0
        moveq   r0, #1

The naive lowering select between two different values. It should recognize the
test is equality test so it's more a conditional move rather than a select:
        cmp     r0, #1
        movne   r0, #0

rdar://9758317


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135017 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 00:42:17 +00:00
Bill Wendling
3641e81172 Assign variable before we test it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135015 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 00:23:39 +00:00