13 Commits

Author SHA1 Message Date
Chad Rosier
e2e26b486d [AArch64] Remove an overly conservative check when generating store pairs.
Store instructions do not modify register values and therefore it's safe
to form a store pair even if the source register has been read in between
the two store instructions.

Previously, the read of w1 (see below) prevented the formation of a stp.

        str      w0, [x2]
        ldr     w8, [x2, #8]
        add      w0, w8, w1
        str     w1, [x2, #4]
        ret

We now generate the following code.

        stp      w0, w1, [x2]
        ldr     w8, [x2, #8]
        add      w0, w8, w1
        ret

All correctness tests with -Ofast on A57 with Spec200x and EEMBC pass.
Performance results for SPEC2K were within noise.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239432 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-09 20:59:41 +00:00
Chad Rosier
676efa4d56 [AArch64] Enhance the load/store optimizer with target-specific alias analysis.
Phabricator: http://reviews.llvm.org/D9863

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237963 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-21 21:36:46 +00:00
Matthias Braun
e4603f0daf MachineInstr: Change return value of getOpcode() to unsigned.
This was previously returning int. However there are no negative opcode
numbers and more importantly this was needlessly different from
MCInstrDesc::getOpcode() (which even is the value returned here) and
SDValue::getOpcode()/SDNode::getOpcode().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237611 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-18 20:27:55 +00:00
Quentin Colombet
05a3f9120a [AArch64][LoadStoreOptimizer] Generate LDP + SXTW instead of LD[U]R + LD[U]RSW.
Teach the load store optimizer how to sign extend a result of a load pair when
it helps creating more pairs.
The rational is that loads are more expensive than sign extensions, so if we
gather some in one instruction this is better!

<rdar://problem/20072968>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231527 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-06 22:42:10 +00:00
Eric Christopher
b99395a7f7 Migrate AArch64 except for TTI and AsmPrinter away from getSubtargetImpl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227293 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-28 03:51:33 +00:00
Quentin Colombet
af1cd03764 [AArch64][LoadStoreOptimizer] Form LDPSW when possible.
This patch adds the missing LD[U]RSW variants to the load store optimizer, so
that we generate LDPSW when possible.

<rdar://problem/19583480>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226978 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-24 01:25:54 +00:00
Jim Grosbach
ce9ccc00d3 Add missing closing namespace comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215402 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-11 22:42:31 +00:00
Eric Christopher
9f85dccfc6 Remove the TargetMachine forwards for TargetSubtargetInfo based
information and update all callers. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214781 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-04 21:25:23 +00:00
Benjamin Kramer
ce63ab327a Run sort_includes.py on the AArch64 backend.
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213938 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-25 11:42:14 +00:00
Tilmann Scheller
45a8d99f59 [AArch64] clang-format the load/store optimizer.
No change in functionality.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210182 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-04 12:40:35 +00:00
Tilmann Scheller
b2caf9766e [AArch64] Fix some LLVM Coding Standards violations in the load/store optimizer.
Variable names should start with an upper case letter.

No change in functionality.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210181 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-04 12:36:28 +00:00
Tilmann Scheller
1514ecc83a [AArch64] Fix typo in load/store optimizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210114 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-03 16:33:13 +00:00
Tim Northover
29f94c7201 AArch64/ARM64: move ARM64 into AArch64's place
This commit starts with a "git mv ARM64 AArch64" and continues out
from there, renaming the C++ classes, intrinsics, and other
target-local objects for consistency.

"ARM64" test directories are also moved, and tests that began their
life in ARM64 use an arm64 triple, those from AArch64 use an aarch64
triple. Both should be equivalent though.

This finishes the AArch64 merge, and everyone should feel free to
continue committing as normal now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-24 12:50:23 +00:00