HandlePHINodesInSuccessorBlocks that works FastISel-style. This
allows PHI nodes to be updated correctly while using FastISel.
This also involves some code reorganization; ValueMap and
MBBMap are now members of the FastISel class, so they needn't
be passed around explicitly anymore. Also, SelectInstructions
is changed to SelectInstruction, and only does one instruction
at a time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55746 91177308-0d34-0410-b5e6-96231b3b80d8
the simple fix, materializing the constant before every use. It might be better to either track domination of uses or
to materialize all constants and the beginning of the function and let remat sort when to do materialization at uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55703 91177308-0d34-0410-b5e6-96231b3b80d8
and SelectionDAGLowering classes, out of SelectionDAGISel.cpp and put
it in a separate file, SelectionDAGBuild.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55701 91177308-0d34-0410-b5e6-96231b3b80d8
The first can update the SDNode in an SDValue
while the second is called with SDNode* and
returns a possibly updated SDNode*.
This patch has no intended functional impact,
but helps eliminating ugly temporary SDValues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55608 91177308-0d34-0410-b5e6-96231b3b80d8
assignment when selecting the def. This is the naive solution to the problem: insert a copy to the pre-chosen
vreg. Other solutions might be preferable, such as:
1) Passing the dest reg into FastEmit_. However, this would require the higher level code to know about reg classes, which they don't currently.
2) Selecting blocks in reverse postorder. This has some compile time cost for computing the order, and we'd need to measure its impact.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55555 91177308-0d34-0410-b5e6-96231b3b80d8
its work by putting all nodes in the worklist, requiring a big
dynamic allocation. Now, DAGCombiner just iterates over the AllNodes
list and maintains a worklist for nodes that are newly created or
need to be revisited. This allows the worklist to stay small in most
cases, so it can be a SmallVector.
This has the side effect of making DAGCombine not miss a folding
opportunity in alloca-align-rounding.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55498 91177308-0d34-0410-b5e6-96231b3b80d8
SelectionDAGLowering instead of being in an anonymous namespace.
This fixes warnings about SelectionDAGLowering having fields
using anonymous namespaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55497 91177308-0d34-0410-b5e6-96231b3b80d8
ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD.
Increased the Hardcoded Constant OpActionsCapacity to match.
Large but boring; no functional change.
This is to support partial-word atomics on ppc; i8 is
not a valid type there, so by the time we get to lowering, the
ATOMIC_LOAD nodes looks the same whether the type was i8 or i32.
The information can be added to the AtomicSDNode, but that is the
largest SDNode; I don't fully understand the SDNode allocation,
but it is sensitive to the largest node size, so increasing
that must be bad. This is the alternative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55457 91177308-0d34-0410-b5e6-96231b3b80d8
works with.
SelectionDAG, FunctionLoweringInfo, and SelectionDAGLowering
objects now get created once per SelectionDAGISel instance, and
can be reused across blocks and across functions. Previously,
they were created and destroyed each time they were needed.
This reorganization simplifies the handling of PHI nodes, and
also SwitchCases, JumpTables, and BitTestBlocks. This
simplification has the side effect of fixing a bug in FastISel
where successor PHI nodes weren't being updated correctly.
This is also a step towards making the transition from FastISel
into and out of SelectionDAG faster, and also making
plain SelectionDAG faster on code with lots of little blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55450 91177308-0d34-0410-b5e6-96231b3b80d8
just try to do the action and let the tablegen-generated code
determine if there is target-support for an operation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55427 91177308-0d34-0410-b5e6-96231b3b80d8
the details of materializing constants and other values into
registers, and make use of it in several places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55426 91177308-0d34-0410-b5e6-96231b3b80d8
of two, and to not need a scratch std::vector. Also, compute the ordering
immediately in the result array, instead of in another scratch std::vector
that is copied to the result array.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55421 91177308-0d34-0410-b5e6-96231b3b80d8
