Commit Graph

30449 Commits

Author SHA1 Message Date
Philip Reames
6025d734a8 [InstCombine] Propagate non-null facts to call parameters
If a parameter to a function is known non-null, use the existing parameter attributes to record that fact at the call site. This has no optimization benefit by itself - that I know of - but is an enabling change for http://reviews.llvm.org/D9129.

Differential Revision: http://reviews.llvm.org/D9132



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239795 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-16 00:43:54 +00:00
Alex Lorenz
00b6413c97 MIR Serialization: Print and parse simple machine function attributes.
This commit serializes the simple, scalar attributes from the 
'MachineFunction' class.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10449


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239790 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-16 00:10:47 +00:00
Alex Lorenz
034945e8fe MIR Serialization: Create dummy functions when the MIR file doesn't have LLVM IR.
This commit creates a dummy LLVM IR function with one basic block and an unreachable
instruction for each parsed machine function when the MIR file doesn't have LLVM IR.
This change is required as the machine function analysis pass creates machine
functions only for the functions that are defined in the current LLVM module.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10135


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239778 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 23:07:38 +00:00
Alex Lorenz
185789e9a0 MIR Serialization: Report an error when machine functions have the same name.
This commit reports an error when the MIR parser encounters a machine
function with the name that is the same as the name of a different
machine function.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10130


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239774 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 22:23:23 +00:00
Peter Collingbourne
9784231221 Add safestack attribute to LLVMAttribute enum and Go bindings. Correct
constants in commented-out part of LLVMAttribute enum. Add tests that verify
that the safestack attribute is only allowed as a function attribute.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239772 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 22:16:51 +00:00
Colin LeMahieu
0d6057a14d [Hexagon] Using readobj rather than objdump.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239770 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 21:57:41 +00:00
Colin LeMahieu
c1344684c9 [Hexagon] PC-relative offsets are relative to packet start rather than the offset of the relocation. Set relocation addend and check it's correct in the ELF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239769 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 21:52:13 +00:00
Simon Pilgrim
b1ce237a80 [X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239767 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 21:49:31 +00:00
Peter Collingbourne
7ffec838a2 Protection against stack-based memory corruption errors using SafeStack
This patch adds the safe stack instrumentation pass to LLVM, which separates
the program stack into a safe stack, which stores return addresses, register
spills, and local variables that are statically verified to be accessed
in a safe way, and the unsafe stack, which stores everything else. Such
separation makes it much harder for an attacker to corrupt objects on the
safe stack, including function pointers stored in spilled registers and
return addresses. You can find more information about the safe stack, as
well as other parts of or control-flow hijack protection technique in our
OSDI paper on code-pointer integrity (http://dslab.epfl.ch/pubs/cpi.pdf)
and our project website (http://levee.epfl.ch).

The overhead of our implementation of the safe stack is very close to zero
(0.01% on the Phoronix benchmarks). This is lower than the overhead of
stack cookies, which are supported by LLVM and are commonly used today,
yet the security guarantees of the safe stack are strictly stronger than
stack cookies. In some cases, the safe stack improves performance due to
better cache locality.

Our current implementation of the safe stack is stable and robust, we
used it to recompile multiple projects on Linux including Chromium, and
we also recompiled the entire FreeBSD user-space system and more than 100
packages. We ran unit tests on the FreeBSD system and many of the packages
and observed no errors caused by the safe stack. The safe stack is also fully
binary compatible with non-instrumented code and can be applied to parts of
a program selectively.

This patch is our implementation of the safe stack on top of LLVM. The
patches make the following changes:

- Add the safestack function attribute, similar to the ssp, sspstrong and
  sspreq attributes.

- Add the SafeStack instrumentation pass that applies the safe stack to all
  functions that have the safestack attribute. This pass moves all unsafe local
  variables to the unsafe stack with a separate stack pointer, whereas all
  safe variables remain on the regular stack that is managed by LLVM as usual.

- Invoke the pass as the last stage before code generation (at the same time
  the existing cookie-based stack protector pass is invoked).

- Add unit tests for the safe stack.

Original patch by Volodymyr Kuznetsov and others at the Dependable Systems
Lab at EPFL; updates and upstreaming by myself.

Differential Revision: http://reviews.llvm.org/D6094

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239761 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 21:07:11 +00:00
Alex Lorenz
a15d888abf MIR Serialization: Connect the machine function analysis pass to the MIR parser.
This commit connects the machine function analysis pass (which creates machine
functions) to the MIR parser, which will initialize the machine functions 
with the state from the MIR file and reconstruct the machine IR.

This commit introduces a new interface called 'MachineFunctionInitializer',
which can be used to provide custom initialization for the machine functions.

This commit also introduces a new diagnostic class called 
'DiagnosticInfoMIRParser' which is used for MIR parsing errors.
This commit modifies the default diagnostic handling in LLVMContext - now the
the diagnostics are printed directly into llvm::errs() so that the MIR parsing 
errors can be printed with colours.  

Reviewers: Justin Bogner

Differential Revision: http://reviews.llvm.org/D9928


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239753 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 20:30:22 +00:00
Sanjoy Das
0f73200fd2 Add "REQUIRES: asserts" to test case that uses -debug-only
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239748 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 20:05:38 +00:00
Sanjoy Das
8d5b28507b [CodeGen] Add a pass to fold null checks into nearby memory operations.
Summary:
This change adds an "ImplicitNullChecks" target dependent pass.  This
pass folds null checks into memory operation using the FAULTING_LOAD
pseudo-op introduced in previous patches.

Depends on D10197
Depends on D10199
Depends on D10200

Reviewers: reames, rnk, pgavlin, JosephTremoulet, atrick

Reviewed By: atrick

Subscribers: ab, JosephTremoulet, llvm-commits

Differential Revision: http://reviews.llvm.org/D10201

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239743 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 18:44:27 +00:00
Evgeny Astigeevich
2ecc72cc58 On behalf of Alexandros Lamprineas:
LLVM targeting aarch64 doesn't correctly produce aligned accesses for non-aligned
data at -O0/fast-isel (-mno-unaligned-access).
The root cause seems to be in fast-isel not producing unaligned access correctly
for -mno-unaligned-access.

The patch just aborts fast-isel for loads and stores when -mno-unaligned-access is
present. 
The regression test is updated to check this new test case (-mno-unaligned-access 
together with fast-isel).

Differential Revision: http://reviews.llvm.org/D10360



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239732 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 15:48:44 +00:00
Rafael Espindola
99e760ad9e gold-plugin: save the .o when given -save-temps.
The plugin now save the bitcode before and after optimizations and the
.o that is passed to the linker.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239726 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 13:36:27 +00:00
Jingyue Wu
7a1e93493d [ValueTracking] do not overwrite analysis results already computed
Summary:
ValueTracking used to overwrite the analysis results computed from
assumes and dominating conditions. This patch fixes this issue.

Test Plan: test/Analysis/ValueTracking/assume.ll

Reviewers: hfinkel, majnemer

Reviewed By: majnemer

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10283

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239718 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 05:46:29 +00:00
Hao Liu
5e1ea386d4 [AArch64] Delete two empty files, which should be removed by r239713.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239715 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 02:56:40 +00:00
Hao Liu
5ab48a2f69 [AArch64] Revert r239711 again. We need to discuss how to share code between AArch64 and ARM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239713 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 01:56:40 +00:00
Hao Liu
6024ab3b8f [AArch64] Match interleaved memory accesses into ldN/stN instructions.
Re-commit after adding "-aarch64-neon-syntax=generic" to fix the failure on OS X.
This patch was firstly committed in r239514, then reverted in r239544 because of a syntax incompatible failure on OS X.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239711 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 01:35:49 +00:00
Benjamin Kramer
49e5e9f0c9 [InstSimplify] fsub nnan x, x -> 0.0 is valid without ninf
Both inf - inf and (-inf) - (-inf) are NaN, so it's already covered by
nnan.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239702 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-14 21:01:20 +00:00
Benjamin Kramer
f3e82660de [InstSimplify] Add self-fdiv identities for -ffinite-math-only.
When NaNs and Infs are ignored we can fold
 X /  X -> 1.0
-X /  X -> -1.0
 X / -X -> -1.0

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239701 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-14 18:53:58 +00:00
Igor Breger
17ae2138b0 AVX-512: Implemented DAG lowering for shuff62x2/shufi62x2 instuctions ( Shuffle Packed Values at 128-bit Granularity )
Tests added , vector-shuffle-512-v8.ll test re-generated.

Differential Revision: http://reviews.llvm.org/D10300

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239697 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-14 13:07:47 +00:00
Michael Kuperstein
3dd555171e Add support for parsing the XOR operator in Intel syntax inline assembly.
Differential Revision: http://reviews.llvm.org/D10385
Patch by marina.yatsina@intel.com


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239695 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-14 12:59:45 +00:00
Igor Breger
6ea3ad7e6e AVX-512: Implemented cvtsi2ss/d cvtusi2ss/d instructions with round control for KNL.
Added intrinsics for cvtsi2ss/d instructions.
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D10430

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239694 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-14 12:44:55 +00:00
Colin LeMahieu
3a36996b73 [Hexagon] Adding some codegen tests and updating some to match spec.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239690 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-13 21:46:39 +00:00
Simon Pilgrim
4692cb1303 [DAGCombiner] Added BSWAP(BSWAP(x)) -> x combine pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239682 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-13 16:25:12 +00:00
Simon Pilgrim
d8b27b1cb1 [DAGCombiner] Added BSWAP vector constant folding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239675 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-13 14:08:15 +00:00
Tom Stellard
953c681473 R600 -> AMDGPU rename
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239657 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-13 03:28:10 +00:00
Tim Northover
31b680fa24 AArch64: map bare-metal arm64-macho triple to MachO MC layer.
Far better than an assertion about expecting ELF.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239647 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-12 23:37:11 +00:00
Tom Stellard
f28da43112 R600/SI: Add assembler support for FLAT instructions
- Add glc, slc, and tfe operands to flat instructions
- Add missing flat instructions
- Fix the encoding of flat_load_dwordx3 and flat_store_dwordx3.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239637 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-12 20:47:06 +00:00
Colin LeMahieu
53aa3e0444 [Hexagon] Making intrinsic tests agnostic to register allocation. Narrowing intrinsic parameters to appropriate width.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239634 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-12 19:57:32 +00:00
Rafael Espindola
a66840f18d Don't depend on the interleaving of stdout and stderr.
That can change as we change the buffering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239602 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-12 12:20:03 +00:00
John Brawn
14d0411acb [ARM] Disabling vfp4 should disable fp16
ARMTargetParser::getFPUFeatures should disable fp16 whenever it
disables vfp4, as otherwise something like -mcpu=cortex-a7 -mfpu=none
leaves us with fp16 enabled (though the only effect that will have is
a wrong build attribute).

Differential Revision: http://reviews.llvm.org/D10397


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239599 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-12 09:38:51 +00:00
Peter Collingbourne
ba74b27ed1 LowerBitSets: Give names to aliases of unnamed bitset element objects.
It is valid for globals to be unnamed, but aliases must have a name. To avoid
creating invalid IR, we need to assign names to any aliases we create that
point to unnamed objects that have been moved into combined globals.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239590 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-12 03:25:05 +00:00
Alexey Samsonov
7168a91de7 [GVN] Use a simpler form of IRBuilder constructor.
Summary:
A side effect of this change is that it IRBuilder now automatically
created debug info locations for new instructions, which is the
same as debug location of insertion point. This is fine for the
functions in questions (GetStoreValueForLoad and
GetMemInstValueForLoad), as they are used in two situations:
  * GVN::processLoad, which tries to eliminate a load. In this case
    new instructions would have the same debug location as the load they
    eventually replace;
  * MaterializeAdjustedValue, which adds new instructions to the end
    of the basic blocks, which could later be used to replace the load
    definition. In this case we don't yet know the way the load would
    be eventually replaced (either by assembling the precomputed values
    via PHI, or by using them directly), so just using the basic block
    strategy seems to be reasonable. There is also a special case
    in the code that *would* adjust the location of the last
    instruction replacing the load definition to the location of the
    load.

Test Plan: regression test suite

Reviewers: echristo, dberlin, dblaikie

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10405

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239585 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-12 01:39:48 +00:00
Reid Kleckner
2bd0221fa4 [WinEH] Put finally pointers in the handler scope table field
We were putting them in the filter field, which is correct for 64-bit
but wrong for 32-bit.

Also switch the order of scope table entry emission so outermost entries
are emitted first, and fix an obvious state assignment bug.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239574 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 23:37:18 +00:00
Reid Kleckner
3e16bd3aaf [WinEH] Create an llvm.x86.seh.exceptioninfo intrinsic
This intrinsic is like framerecover plus a load. It recovers the EH
registration stack allocation from the parent frame and loads the
exception information field out of it, giving back a pointer to an
EXCEPTION_POINTERS struct. It's designed for clang to use in SEH filter
expressions instead of accessing the EXCEPTION_POINTERS parameter that
is available on x64.

This required a minor change to MC to allow defining a label variable to
another absolute framerecover label variable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239567 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 22:32:23 +00:00
Peter Collingbourne
6170134a1f Object: Prepend __imp_ when mangling a dllimport symbol in IRObjectFile.
We cannot prepend __imp_ in the IR mangler because a function reference may
be emitted unmangled in a constant initializer. The linker is expected to
resolve such references to thunks. This is covered by the new test case.

Strictly speaking we ought to emit two undefined symbols, one with __imp_ and
one without, as we cannot know which symbol the final object file will refer
to. However, this would require rather intrusive changes to IRObjectFile,
and lld works fine without it for now.

This reimplements r239437, which was reverted in r239502.

Differential Revision: http://reviews.llvm.org/D10400

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239560 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 21:42:18 +00:00
Alexey Samsonov
bc482286fc Set proper debug location for branch added in BasicBlock::splitBasicBlock().
This improves debug locations in passes that do a lot of basic block
transformations. Important case is LoopUnroll pass, the test for correct
debug locations accompanies this change.

Test Plan: regression test suite

Reviewers: dblaikie, sanjoy

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10367

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239551 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 18:25:54 +00:00
Rafael Espindola
688e7b3049 This reverts commit r239529 and r239514.
Revert "[AArch64] Match interleaved memory accesses into ldN/stN instructions."
Revert "Fixing MSVC 2013 build error."

The  test/CodeGen/AArch64/aarch64-interleaved-accesses.ll test was failing on OS X.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239544 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 17:30:33 +00:00
Reid Kleckner
cd354fa84d Revert "Fix merges of non-zero vector stores"
This reverts commit r239539.

It was causing SDAG assertions while building freetype.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239543 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 17:25:24 +00:00
Matt Arsenault
b1d220c21a SLSR: Pass address space to isLegalAddressingMode
This only updates one of the uses. The other is used in cases
that may never touch memory, so I'm not sure why this is even
calling it. Perhaps there should be a new, similar hook for such
cases or pass -1 for unknown address space.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239540 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 16:13:39 +00:00
Matt Arsenault
564ff6478c Fix merges of non-zero vector stores
Now actually stores the non-zero constant instead of 0.
I somehow forgot to include this part of r238108.

The test change was just an independent instruction order swap,
so just add another check line to satisfy CHECK-NEXT.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239539 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 16:03:52 +00:00
Tom Stellard
6fcf906bb0 R600/SI: Add -mcpu=bonaire to a test that uses flat address space
Flat instructions don't exist on SI, but there is a bug in the backend that
allows them to be selected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239533 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 14:51:46 +00:00
Toma Tabacu
f24e4e46cd Recommit "[mips] [IAS] Add support for BNE and BEQ with an immediate operand." (r239396).
Apparently, Arcanist didn't include some of my local changes in my previous
commit attempt.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239523 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 10:36:10 +00:00
Zoran Jovanovic
9d115effdf [mips][microMIPS] Implement ERET and ERETNC instructions
http://reviews.llvm.org/D10091


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239522 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 10:22:46 +00:00
Zoran Jovanovic
d09e8beec3 [mips] Change existing uimm10 operand to restrict the accepted immediates
http://reviews.llvm.org/D10312


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239520 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 09:51:58 +00:00
Zoran Jovanovic
938cba6ae3 [mips][microMIPSr6] Change disassembler tests to one line format
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239519 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 09:42:10 +00:00
Hao Liu
442f620296 [AArch64] Match interleaved memory accesses into ldN/stN instructions.
Add a pass AArch64InterleavedAccess to identify and match interleaved memory accesses. This pass transforms an interleaved load/store into ldN/stN intrinsic. As Loop Vectorizor disables optimization on interleaved accesses by default, this optimization is also disabled by default. To enable it by "-aarch64-interleaved-access-opt=true"

E.g. Transform an interleaved load (Factor = 2):
       %wide.vec = load <8 x i32>, <8 x i32>* %ptr
       %v0 = shuffle %wide.vec, undef, <0, 2, 4, 6>  ; Extract even elements
       %v1 = shuffle %wide.vec, undef, <1, 3, 5, 7>  ; Extract odd elements
     Into:
       %ld2 = { <4 x i32>, <4 x i32> } call aarch64.neon.ld2(%ptr)
       %v0 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 0
       %v1 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 1

E.g. Transform an interleaved store (Factor = 2):
       %i.vec = shuffle %v0, %v1, <0, 4, 1, 5, 2, 6, 3, 7>  ; Interleaved vec
       store <8 x i32> %i.vec, <8 x i32>* %ptr
     Into:
       %v0 = shuffle %i.vec, undef, <0, 1, 2, 3>
       %v1 = shuffle %i.vec, undef, <4, 5, 6, 7>
       call void aarch64.neon.st2(%v0, %v1, %ptr)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239514 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 09:05:02 +00:00
Simon Pilgrim
44226ffc19 [X86][SSE] Vectorized i8 and i16 shift operators
This patch ensures that SHL/SRL/SRA shifts for i8 and i16 vectors avoid scalarization. It builds on the existing i8 SHL vectorized implementation of moving the shift bits up to the sign bit position and separating the 4, 2 & 1 bit shifts with several improvements:

1 - SSE41 targets can use (v)pblendvb directly with the sign bit instead of performing a comparison to feed into a VSELECT node.
2 - pre-SSE41 targets were masking + comparing with an 0x80 constant - we avoid this by using the fact that a set sign bit means a negative integer which can be compared against zero to then feed into VSELECT, avoiding the need for a constant mask (zero generation is much cheaper).
3 - SRA i8 needs to be unpacked to the upper byte of a i16 so that the i16 psraw instruction can be correctly used for sign extension - we have to do more work than for SHL/SRL but perf tests indicate that this is still beneficial.

The i16 implementation is similar but simpler than for i8 - we have to do 8, 4, 2 & 1 bit shifts but less shift masking is involved. SSE41 use of (v)pblendvb requires that the i16 shift amount is splatted to both bytes however.

Tested on SSE2, SSE41 and AVX machines.

Differential Revision: http://reviews.llvm.org/D9474

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239509 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 07:46:37 +00:00
Nemanja Ivanovic
f7d6501d1d LLVM support for vector quad bit permute and gather instructions through builtins
This patch corresponds to review:
http://reviews.llvm.org/D10096

This is the back end portion of the patch related to D10095.
The patch adds the instructions and back end intrinsics for:
vbpermq
vgbbd


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239505 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 06:21:25 +00:00