33841 Commits

Author SHA1 Message Date
Colin LeMahieu
60b4c7fc30 [Hexagon] Adding functionality for duplexing. Duplexing is a way to compress commonly used pairs of instructions in order to reduce code size. The test case duplex.ll normally would be 8 bytes, assign register to 0 and jump to link register. After duplexing this is only 4 bytes. This also tests the HexagonMCShuffler code path which is used to make sure duplexed instructions still follow slot requirements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239095 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 21:16:16 +00:00
Jingyue Wu
7c65b1bfb2 Revert r239082
llc crashed for NVPTX backend


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239094 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 21:07:08 +00:00
Ahmed Bougacha
0d9335eda7 [GlobalMerge] Take into account minsize on Global users' parents.
Now that we can look at users, we can trivially do this: when we would
have otherwise disabled GlobalMerge (currently -O<3), we can just run
it for minsize functions, as it's usually a codesize win.

Differential Revision: http://reviews.llvm.org/D10054


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239087 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 20:39:23 +00:00
Jim Grosbach
aa48bf4e1c MC: Remove obsolete MachO UseAggressiveSymbolFolding.
Fix the FIXME and remove this old as(1) compat option. It was useful for
bringup of the integrated assembler to diff object files, but now it's
just causing more relocations than strictly necessary to be generated.

rdar://21201804

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239084 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 20:27:42 +00:00
Jingyue Wu
81fb217d91 [NVPTX] kernel pointer arguments point to the global address space
Summary:
With this patch, NVPTXLowerKernelArgs converts a kernel pointer argument to a
pointer in the global address space. This change, along with
NVPTXFavorNonGenericAddrSpaces, allows the NVPTX backend to emit ld.global.*
and st.global.* for accessing kernel pointer arguments.

Minor changes:
1. refactor: extract function convertToPointerInAddrSpace
2. fix a bug in the test case in bug21465.ll

Test Plan: lower-kernel-ptr-arg.ll

Reviewers: eliben, meheff, jholewinski

Reviewed By: jholewinski

Subscribers: wengxt, jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D10154

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239082 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 20:19:38 +00:00
Alexei Starovoitov
ac73683b10 [bpf] add big- and host- endian support
Summary:
-march=bpf    -> host endian
-march=bpf_le -> little endian
-match=bpf_be -> big endian

Test Plan:
v1 was tested by IBM s390 guys and appears to be working there.
It bit rots too fast here.

Reviewers: chandlerc, tstellarAMD

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10177

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239071 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 19:15:05 +00:00
Matt Arsenault
35cc03a1ea R600/SI: Reimplement isLegalAddressingMode
Now that we sometimes know the address space, this can
theoretically do a better job.

This needs better test coverage, but this mostly depends on
first updating the loop optimizatiosn to provide the address
space.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239053 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 16:17:42 +00:00
Matt Arsenault
e0d4034b76 R600/SI: Fix some cases for load / store of half
Mostly argument loads were producing broken zextloads
from an FP type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239049 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 16:00:27 +00:00
Benjamin Kramer
7ec7c7d865 Replace custom fixed endian to raw_ostream emission with EndianStream.
Less code, clearer and more efficient. No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239040 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 15:03:02 +00:00
Daniel Sanders
6ff6fc6055 Replace string GNU Triples with llvm::Triple in MCAsmInfo subclasses and create*AsmInfo(). NFC.
Summary:
This is the first of several patches to eliminate StringRef forms of GNU
triples from the internals of LLVM. After this is complete, GNU triples
will be replaced by a more authoratitive representation in the form of
an LLVM TargetTuple.

Reviewers: rengolin

Reviewed By: rengolin

Subscribers: ted, llvm-commits, rengolin, jholewinski

Differential Revision: http://reviews.llvm.org/D10236


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239036 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 13:12:25 +00:00
Elena Demikhovsky
0880fe5997 AVX-512: I brought back vector-shuffle-512-v8.ll test.
I re-generated it after all AVX-512 shuffle optimizations.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239026 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 07:49:56 +00:00
Elena Demikhovsky
1bbb64b206 AVX-512: added all SKX forms of VPERMW/D/Q instructions.
Added all forms of VPERMPS/PD instrcuctions.
Added encoding tests.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239016 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 07:07:13 +00:00
Elena Demikhovsky
693d40eec0 Removed {}, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239014 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 07:01:29 +00:00
Rafael Espindola
cddcabadf2 Bring back r239006 with a fix.
The fix is just that getOther had not been updated for packing the st_other
values in fewer bits and could return spurious values:

-  unsigned Other = (getFlags() & (0x3f << ELF_STO_Shift)) >> ELF_STO_Shift;
+  unsigned Other = (getFlags() & (0x7 << ELF_STO_Shift)) >> ELF_STO_Shift;

Original message:

Pack the MCSymbolELF bit fields into MCSymbol's Flags.

This reduces MCSymolfELF from 64 bytes to 56 bytes on x86_64.

While at it, also make getOther/setOther easier to use by accepting unshifted
STO_* values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239012 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 05:59:23 +00:00
Rafael Espindola
64a82a3d70 Revert "Pack the MCSymbolELF bit fields into MCSymbol's Flags."
This reverts commit r239006.

I am debugging the powerpc failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239010 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 05:00:12 +00:00
Rafael Espindola
d90fd082f9 Pack the MCSymbolELF bit fields into MCSymbol's Flags.
This reduces MCSymolfELF from 64 bytes to 56 bytes on x86_64.

While at it, also make getOther/setOther easier to use by accepting unshifted
STO_* values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239006 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 02:32:20 +00:00
Sanjay Patel
e4e5cf5a66 make reciprocal estimate code generation more flexible by adding command-line options (3rd try)
The first try (r238051) to land this was reverted due to ExecutionEngine build failure;
that was hopefully addressed by r238788.

The second try (r238842) to land this was reverted due to BUILD_SHARED_LIBS failure;
that was hopefully addressed by r238953.

This patch adds a TargetRecip class for processing many recip codegen possibilities.
The class is intended to handle both command-line options to llc as well
as options passed in from a front-end such as clang with the -mrecip option.

The x86 backend is updated to use the new functionality.
Only -mcpu=btver2 with -ffast-math should see a functional change from this patch.
All other x86 CPUs continue to *not* use reciprocal estimates by default with -ffast-math.

Differential Revision: http://reviews.llvm.org/D8982



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239001 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 01:32:35 +00:00
Tom Stellard
8c009e3943 R600: Re-enable sub-reg liveness
The bug in the R600 backend that this uncovered has been fixed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238999 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 01:20:04 +00:00
Rafael Espindola
c212856f78 Remove MCELFSymbolFlags.h. It is now internal to MCSymbolELF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238996 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 00:47:43 +00:00
Rafael Espindola
4ce10b56e6 Remove getOrCreateSymbolData. There is no MCSymbolData anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238952 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-03 19:03:11 +00:00
Colin LeMahieu
0a999e4d3a [Hexagon] Test doesn't work on all platforms. At any rate the uninitialized variable issue was fixed. Removing re-registering ASM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238949 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-03 18:00:45 +00:00
Colin LeMahieu
4009e89061 [Hexagon] Reapply 238772 OSABI was not correctly set, added empty_elf test to make sure it is.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238947 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-03 17:34:16 +00:00
Matthias Braun
e942914d29 ARM: Thumb2 LDRD/STRD supports independent input/output regs
The existing code would unnecessarily break LDRD/STRD apart with
non-adjacent registers, on thumb2 this is not necessary.

Ideally on thumb2 we shouldn't match for ldrd/strd pre-regalloc anymore
as there is not reason to set register hints anymore, changing that is
something for a future patch however.

Differential Revision: http://reviews.llvm.org/D9694

Recommiting after the revert in r238821, the buildbot still failed with
the patch removed so there seems to be another reason for the breakage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238935 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-03 16:30:24 +00:00
Daniel Sanders
a57c862c9d [arm] Fix r238921. We must handle Constraint_i too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238925 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-03 14:17:18 +00:00
Asaf Badouh
ce375dc63a re-apply 238809
AVX-512: Implemented GETEXP instruction for KNL and SKX
Added rounding mode modifier for SQRTPS/PD
Added tests for encoding and intrinsics.
CR:
http://reviews.llvm.org/D9991


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238923 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-03 13:41:48 +00:00
Daniel Sanders
b0e7aeb694 [arm] Distinguish the /U[qytnms]/, 'Uv', 'Q', and 'm' inline assembly memory constraints.
Summary:
But still handle them the same way since I don't know how they differ on
this target.

Of these, /U[qytnms]/ do not have backend tests but are accepted by clang.

No functional change intended.

Reviewers: t.p.northover

Reviewed By: t.p.northover

Subscribers: t.p.northover, aemerson, llvm-commits

Differential Revision: http://reviews.llvm.org/D8203


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238921 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-03 12:33:56 +00:00
Elena Demikhovsky
fc28da72f0 AVX-512: More code improvements in shuffles, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238919 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-03 12:05:03 +00:00
Elena Demikhovsky
10eb2dd9df AVX-512: VSHUFPD instruction selection - code improvements
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238918 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-03 11:21:01 +00:00
Elena Demikhovsky
23dc4bbf1d AVX-512: Implemented SHUFF32x4/SHUFF64x2/SHUFI32x4/SHUFI64x2 instructions for SKX and KNL.
Added tests for encoding.

By Igor Breger (igor.breger@intel.com)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238917 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-03 10:56:40 +00:00
Elena Demikhovsky
49659f6378 X86: Added MPX feature and bound registers.
Intel® Memory Protection Extensions (Intel® MPX) is a new feature in Skylake.
It is a part of KNL and SKX sets. It is also a part of Skylake client.

I added definition of %bnd0 - %bnd3 registers, each register is a pair of 64-bit integers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238916 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-03 10:30:57 +00:00
Simon Pilgrim
dd5cde6e60 [X86] Removed (unused) FSRL x86 operation
This patch removes the old X86ISD::FSRL op - which allowed float vectors to use the byte right shift operations (causing a domain switch....).

Since the refactoring of the shuffle lowering code this no longer has any use.

Differential Revision: http://reviews.llvm.org/D10169

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238906 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-03 08:32:36 +00:00
Rafael Espindola
a0bcb4184b Revert "make reciprocal estimate code generation more flexible by adding command-line options (2nd try)"
This reverts commit r238842.

It broke -DBUILD_SHARED_LIBS=ON build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238900 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-03 05:32:44 +00:00
Rafael Espindola
2bff0d30f8 Avoid a call to getOrCreateSymbol when we already have the symbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238890 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-03 00:02:40 +00:00
Rafael Espindola
4cc59a13c7 Pass a MCSymbolELF to a few ELF only functions. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238868 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 21:30:13 +00:00
Rafael Espindola
569f382a46 Merge MCELF.h into MCSymbolELF.h.
Now that we have a dedicated type for ELF symbol, these helper functions can
become member function of MCSymbolELF.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238864 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 20:38:46 +00:00
Tim Northover
33d75a269c AArch64: fix typo in SMIN far atomics and add tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238858 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 18:37:20 +00:00
Benjamin Kramer
5a04f4af36 Push constness through LoopInfo::isLoopHeader and clean it up a bit.
NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238843 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 15:28:27 +00:00
Sanjay Patel
871beb8dd7 make reciprocal estimate code generation more flexible by adding command-line options (2nd try)
The first try (r238051) to land this was reverted due to bot failures
that were hopefully addressed by r238788.

This patch adds a TargetRecip class for processing many recip codegen possibilities.
The class is intended to handle both command-line options to llc as well
as options passed in from a front-end such as clang with the -mrecip option.

The x86 backend is updated to use the new functionality.
Only -mcpu=btver2 with -ffast-math should see a functional change from this patch.
All other x86 CPUs continue to *not* use reciprocal estimates by default with -ffast-math.

Differential Revision: http://reviews.llvm.org/D8982



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238842 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 15:28:15 +00:00
Elena Demikhovsky
6628cb50bd AVX-512: Implemented VRANGESD and VRANGESS instructions for SKX Implemented DAG lowering for all these forms.
Added tests for encoding.

By Igor Breger (igor.breger@intel.com)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238834 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 14:12:54 +00:00
Elena Demikhovsky
ccbc17f896 AVX-512: Shorten implementation of lowerV16X32VectorShuffle()
using lowerVectorShuffleWithSHUFPS() and other shuffle-helpers routines.
Added matching of VALIGN instruction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238830 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 13:43:18 +00:00
Vasileios Kalintiris
330e5f16d1 [mips] Add support for dynamic stack realignment.
Summary:
With this change we are able to realign the stack dynamically, whenever it
contains objects with alignment requirements that are larger than the
alignment specified from the given ABI.

We have to use the $fp register as the frame pointer when we perform
dynamic stack realignment. In complex stack frames, with variably-sized
objects, we reserve additionally the callee-saved register $s7 as the
base pointer in order to reference locals.

Reviewers: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8633

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238829 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 13:14:46 +00:00
Renato Golin
6b35bec8ef Revert "ARM: Thumb2 LDRD/STRD supports independent input/output regs"
This reverts commit r238795, as it broke the Thumb2 self-hosting buildbot.

Since self-hosting issues with Clang are hard to investigate, I'm taking the
liberty to revert now, so we can investigate it offline.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238821 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 11:47:30 +00:00
Vladimir Sukharev
1e7e9b1881 [AArch64] Add v8.1a atomic instructions
Patch by: Tom Coxon

Reviewers: t.p.northover

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8501


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238818 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 10:58:41 +00:00
Toma Tabacu
a5f14070fa [mips] [IAS] Add support for the .set softfloat/hardfloat directives.
Summary: These directives are used to set the current value of the SoftFloat feature.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits, mpf

Differential Revision: http://reviews.llvm.org/D9074

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238813 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 09:48:04 +00:00
Elena Demikhovsky
d929045eb5 AVX-512: Implemented VFIXUPIMMSD and VFIXUPIMMSS instructions for KNL
Implemented DAG lowering for all these forms.
Added tests for encoding.

By Igor Breger (igor.breger@intel.com)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238811 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 08:28:57 +00:00
Asaf Badouh
aa9e1c528b revert 238809
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238810 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 07:45:19 +00:00
Asaf Badouh
82fa06895e AVX-512: Implemented GETEXP instruction for KNL and SKX
Added rounding mode modifier for SQRTPS/PD
Added tests for encoding and intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238809 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 07:18:14 +00:00
Rafael Espindola
f7e0685b9a Create a MCSymbolELF.
This create a MCSymbolELF class and moves SymbolSize since only ELF
needs a size expression.

This reduces the size of MCSymbol from 56 to 48 bytes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238801 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 00:25:12 +00:00
Matthias Braun
d421582e90 ARM: Thumb2 LDRD/STRD supports independent input/output regs
The existing code would unnecessarily break LDRD/STRD apart with
non-adjacent registers, on thumb2 this is not necessary.

Ideally on thumb2 we shouldn't match for ldrd/strd pre-regalloc anymore
as there is not reason to set register hints anymore, changing that is
something for a future patch however.

Differential Revision: http://reviews.llvm.org/D9694

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238795 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-01 23:27:08 +00:00
Matthias Braun
fe1391f07d AArch64: Use CMP;CCMP sequences for and/or/setcc trees.
Previously CCMP/FCCMP instructions were only used by the
AArch64ConditionalCompares pass for control flow. This patch uses them
for SELECT like instructions as well by matching patterns in ISelLowering.

PR20927, rdar://18326194

Differential Revision: http://reviews.llvm.org/D8232

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238793 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-01 22:31:17 +00:00