Commit Graph

104083 Commits

Author SHA1 Message Date
Zoran Jovanovic
61e341e0bf [mips][mips64r6] Add Relocations R_MIPS_PCHI16, R_MIPS_PCLO16
Differential Revision: http://reviews.llvm.org/D3860


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209659 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 14:58:51 +00:00
Amara Emerson
87d192bb72 [ARM] Emit correct build attributes for the relocation models.
Patch by Asiri Rathnayake.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209656 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 13:30:21 +00:00
Zoran Jovanovic
f7744906f0 [mips][mips64r6] Add relocations R_MIPS_PC21_S2, R_MIPS_PC26_S2
Differential Revision: http://reviews.llvm.org/D3824


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209655 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 12:55:40 +00:00
Evgeniy Stepanov
18b6fb9612 [asancov] Emit an initializer passing number of coverage code locations in each module.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209654 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 12:39:31 +00:00
Tim Northover
c74a70df6d AArch64: implement copies to/from NZCV as a last ditch effort.
A test in test/Generic creates a DAG where the NZCV output of an ADCS is used
by multiple nodes. This makes LLVM want to save a copy of NZCV for later, which
it couldn't do before.

This should be the last fix required for the aarch64 buildbot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209651 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 12:16:02 +00:00
Tim Northover
e43c5023fe ARM: teach AAPCS-VFP to deal with Cortex-M4.
Cortex-M4 only has single-precision floating point support, so any LLVM
"double" type will have been split into 2 i32s by now. Fortunately, the
consecutive-register framework turns out to be precisely what's needed to
reconstruct the double and follow AAPCS-VFP correctly!

rdar://problem/17012966

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209650 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 10:43:38 +00:00
Daniel Jasper
ae85c73d4a Fix bad assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209648 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 09:55:37 +00:00
Tim Northover
9bbb4066f8 AArch64: support 'c' and 'n' inline asm modifiers.
These are tested by test/CodeGen/Generic, so we should probably know
how to deal with them. Fortunately generic code does it if asked.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209646 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 07:37:21 +00:00
Dinesh Dwivedi
f31b009b3e Adding testcase for PR18886.
Differential Revision: http://reviews.llvm.org/D3837



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209645 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 06:44:25 +00:00
Filipe Cabecinhas
c5f611404c Convert some X86 blendv* intrinsics into IR.
Summary:
Implemented an InstCombine transformation that takes a blendv* intrinsic
call and translates it into an IR select, if the mask is constant.

This will eventually get lowered into blends with immediates if possible,
or pblendvb (with an option to further optimize if we can transform the
pblendvb into a blend+immediate instruction, depending on the selector).
It will also enable optimizations by the IR passes, which give up on
sight of the intrinsic.

Both the transformation and the lowering of its result to asm got shiny
new tests.

The transformation is a bit convoluted because of blendvp[sd]'s
definition:

Its mask is a floating point value! This forces us to convert it and get
the highest bit. I suppose this happened because the mask has type
__m128 in Intel's intrinsic and v4sf (for blendps) in gcc's builtin.

I will send an email to llvm-dev to discuss if we want to change this or
not.

Reviewers: grosbach, delena, nadav

Differential Revision: http://reviews.llvm.org/D3859

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209643 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 03:42:20 +00:00
Rafael Espindola
b84ced649e Fix link.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209640 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-26 21:30:40 +00:00
Rafael Espindola
ce5ddbab6d Use existing helper function.
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209639 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-26 19:57:55 +00:00
Rafael Espindola
f2928b9b5f [PPC] Use alias symbols in address computation.
This seems to match what gcc does for ppc and what every other llvm
backend does.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209638 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-26 19:08:19 +00:00
Tim Northover
e0c2787cb7 AArch64: force i1 to be zero-extended at an ABI boundary.
This commit is debatable. There are two possible approaches, neither
of which is really satisfactory:

1. Use "@foo(i1 zeroext)" to mean an extension to 32-bits on Darwin,
   and 8 bits otherwise.
2. Redefine "@foo(i1)" to mean that the i1 is extended by the caller
   to 8 bits. This goes against the spirit of "zeroext" I think, but
   it's a bit of a vague construct anyway (by definition you're going
   to extend to the amount required by the ABI, that's why it's the
   ABI!).

This implements option 2. The DAG machinery really isn't setup for the
first (there's a fairly strong assumption that "zeroext" goes to at
least the smallest register size), and even if it was the resulting
DAG looks like it would be inferior in many cases.

Theoretically we could add AssertZext nodes in the consumers of
ABI-passed values too now, but this actually seems to make the code
worse in practice by making truncation proceed in two steps. The code
produced is equally valid if we continue to assume only the low bit is
defined.

Should fix PR19850

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209637 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-26 17:22:07 +00:00
Tim Northover
4146695fb2 AArch64: simplify calling conventions slightly.
We can eliminate the custom C++ code in favour of some TableGen to
check the same things. Functionality should be identical, except for a
buffer overrun that was present in the C++ code and meant webkit
failed if any small argument needed to be passed on the stack.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209636 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-26 17:21:53 +00:00
Michael Zolotukhin
90e79a50bb Some cleanup for r209568.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209634 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-26 14:49:46 +00:00
Rafael Espindola
1322e998c1 Convert a few loops to use ranges.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209628 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-26 13:38:51 +00:00
Tilmann Scheller
7aac65de51 [AArch64] Add store + add folding regression tests for the load/store optimization pass.
Add tests for the following transform:

 str X, [x0, #32]
  ...
 add x0, x0, #32
  ->
 str X, [x0, #32]!

with X being either w1, x1, s0, d0 or q0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209627 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-26 13:36:47 +00:00
Tilmann Scheller
3390e6c4a8 [AArch64] Add more regression tests for the load/store optimization pass.
Cover the following cases:

  ldr X, [x0, #32]
   ...
  add x0, x0, #32
   ->
  ldr X, [x0, #32]!

with X being either w1, x1, s0, d0 or q0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209624 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-26 12:15:51 +00:00
Kostya Serebryany
3d150e08ae [asan] decrease asan-instrumentation-with-call-threshold from 10000 to 7000, see PR17409
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209623 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-26 11:57:16 +00:00
Tim Northover
29682f428e AArch64: remove empty ARM64 directories from svn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209621 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-26 11:25:33 +00:00
Tilmann Scheller
852c0cc64f Remove accidentally committed whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209619 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-26 09:40:40 +00:00
Tilmann Scheller
47e3b43768 [AArch64] Add a regression test for the load store optimizer.
We have a couple of regression tests for load/store pairing, but (to my knowledge) there are no regression tests for the load/store + add/sub folding.

As a first step towards increased test coverage of this area, this commit adds a test for one instance of a load + add to pre-indexed load transformation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209618 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-26 09:37:19 +00:00
Owen Anderson
866ed7f63f Make the LoopRotate pass's maximum header size configurable both programmatically
and via the command line, mirroring similar functionality in LoopUnroll.  In
situations where clients used custom unrolling thresholds, their intent could
previously be foiled by LoopRotate having a hardcoded threshold.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209617 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-26 08:58:51 +00:00
David Blaikie
bcc96923e0 DebugInfo: Test linkonce-odr functions under LTO.
This was previously regressed/broken by r192749 (reverted due to this
issue in r192938) and I was about to break it again by accident with
some more invasive changes that deal with the subprogram lists. So to
avoid that and further issues - here's a test.

It's a pretty basic test - in both r192749 and my impending case, this
test would crash, but checking the basics (that we put a subprogram in
just one of the two CUs) seems like a good start.

We still get this wrong in weird ways if the linkonce-odr function
happens to not be identical in the metadata (because it's defined in two
different files (hence the # line directives in this test), etc) even
though it meets the language requirements (identical token stream) for
such a thing. That results in two subprogram DIEs, but only one of them
gets the parameter and high/low pc information, etc. We probably need to
use the DIRef infrastructure to deduplicate functions as we do types to
address this issue - or perhaps teach the BC linker to remove the
duplicate entries in subprogram lists?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209614 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-26 06:44:52 +00:00
David Blaikie
041b4abc73 DwarfUnit: Remove some misleading no-op code introduced in r204162.
Post commit review feedback from Manman called this out, but it looks
like it slipped through the cracks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209611 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-26 05:32:21 +00:00
Rafael Espindola
524b8836c2 Just check the entire string.
Thanks to David Blaikie for the suggestion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209610 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-26 04:08:51 +00:00
NAKAMURA Takumi
a1b1165f30 Reformat linefeeds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209609 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-26 00:25:26 +00:00
NAKAMURA Takumi
a9b0742276 Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209608 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-26 00:25:09 +00:00
Saleem Abdulrasool
d29bdc72bb tools: avoid use of std::function
Remove the use of the std::function and replace the capturing lambda with a
non-capturing one, opting to pass the user data down to the context.  This is
needed as std::function is not yet available on all hosted platforms (it
requires RTTI, which breaks on Windows).

Thanks to Nico Rieck for pointing this out!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209607 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-25 21:37:59 +00:00
Saleem Abdulrasool
b6a667f033 tools: split out Win64EHDumper from COFFDumper
Move the implementation of the Win64 EH printer from the COFFDumper into its own
class.  This is in preparation for adding support to print ARM EH information.
The only real change here is in printUnwindInfo where we now lambda lift the
implicit this parameter for the resolveFunction.  Also setup the printing to
handle ARM.  This now has set the stage to introduce ARM EH printing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209606 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-25 20:26:45 +00:00
Saleem Abdulrasool
53046f3c5f tools: inline simple single-use function
This inlines the single use function in preparation for splitting the Win64EH
printing out of the COFFDumper into its own entity.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209605 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-25 20:26:40 +00:00
Saleem Abdulrasool
ec944ceaf5 tools: refactor COFFDumper symbol resolution logic
Make the use of the cache more transparent to the users.  There is no reason
that the cached entries really need to be passed along.  The overhead for doing
so is minimal: a single extra parameter.  This requires that some standalone
functions be brought into the COFFDumper class so that they may access the
cache.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209604 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-25 20:26:37 +00:00
Saleem Abdulrasool
12d17f4375 tools: use references rather than out pointers in COFFDumper
Switch to use references for parameters that are guaranteed to be non-null.
Simplifies the code a slight bit in preparation for another change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209603 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-25 20:26:33 +00:00
David Blaikie
cec37248b2 DebugInfo: Fix inlining with #file directives a little harder
Seems my previous fix was insufficient - we were still not adding the
inlined function to the abstract scope list. Which meant it wasn't
flagged as inline, didn't have nested lexical scopes in the abstract
definition, and didn't have abstract variables - so the inlined variable
didn't reference an abstract variable, instead being described
completely inline.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209602 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-25 18:11:35 +00:00
David Blaikie
7e79a350b5 Streamline test case by avoiding a temporary file and piping llc output straight to llvm-dwarfdump
We still do temporary files in many cases, just updating this particular
one because I was debugging it and made this change while doing so.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209601 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-25 15:38:52 +00:00
Rafael Espindola
c385367909 Emit data or code export directives based on the type.
Currently we look at the Aliasee to decide what type of export
directive to use. It seems better to use the type of the alias
directly. This is similar to how we handle the alias having the
same address but other attributes (linkage, visibility) from the
aliasee.

With this patch it is now possible to do things like

target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-pc-windows-msvc"
@foo = global [6 x i8] c"\B8*\00\00\00\C3", section ".text", align 16
@f = dllexport alias i32 (), [6 x i8]* @foo
!llvm.module.flags = !{!0}
!0 = metadata !{i32 6, metadata !"Linker Options", metadata !1}
!1 = metadata !{metadata !2, metadata !3}
!2 = metadata !{metadata !"/DEFAULTLIB:libcmt.lib"}
!3 = metadata !{metadata !"/DEFAULTLIB:oldnames.lib"}

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209600 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-25 12:49:07 +00:00
Rafael Espindola
fba226fc52 Make these CHECKs a bit more strict.
The " at the end of the line makes sure we matched the entire directive.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209599 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-25 12:43:13 +00:00
Peter Collingbourne
62692b442a Add an extension point for peephole optimizers.
This extension point allows adding passes that perform peephole optimizations
similar to the instruction combiner. These passes will be inserted after
each instance of the instruction combiner pass.

Differential Revision: http://reviews.llvm.org/D3905

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209595 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-25 10:27:02 +00:00
Hans Wennborg
68b0d1d2b4 Fix some misplaced spaces around 'override'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209589 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-24 20:19:40 +00:00
Saleem Abdulrasool
11d505b678 build: sort llvm-readobj sources
Sort the source files.  NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209587 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-24 20:04:21 +00:00
Saleem Abdulrasool
a054d531d7 llvm-readobj: remove some dead code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209586 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-24 19:54:28 +00:00
Tim Northover
0fc41252ba AArch64: disable FastISel for large code model.
The code emitted is what would be expected for the small model, so it
shouldn't be used when objects can be the full 64-bits away.

This fixes MCJIT tests on Linux.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209585 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-24 19:45:41 +00:00
Benjamin Kramer
c734d38c7c MachineVerifier: Clean up some syntactic weirdness left behind by find&replace.
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209581 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-24 13:31:10 +00:00
Benjamin Kramer
9d934aca34 CodeGen: Make MachineBasicBlock::back skip to the beginning of the last bundle.
This makes front/back symmetric with begin/end, avoiding some confusion.
Added instr_front/instr_back for the old behavior, corresponding to
instr_begin/instr_end. Audited all three in-tree users of back(), all
of them look like they don't want to look inside bundles.

Fixes an assertion (PR19815) when generating debug info on mips, where a
delay slot was bundled at the end of a branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209580 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-24 13:13:17 +00:00
Tim Northover
29f94c7201 AArch64/ARM64: move ARM64 into AArch64's place
This commit starts with a "git mv ARM64 AArch64" and continues out
from there, renaming the C++ classes, intrinsics, and other
target-local objects for consistency.

"ARM64" test directories are also moved, and tests that began their
life in ARM64 use an arm64 triple, those from AArch64 use an aarch64
triple. Both should be equivalent though.

This finishes the AArch64 merge, and everyone should feel free to
continue committing as normal now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-24 12:50:23 +00:00
Tim Northover
9105f66d6f AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.
I'm doing this in two phases for a better "git blame" record. This
commit removes the previous AArch64 backend and redirects all
functionality to ARM64. It also deduplicates test-lines and removes
orphaned AArch64 tests.

The next step will be "git mv ARM64 AArch64" and rewire most of the
tests.

Hopefully LLVM is still functional, though it would be even better if
no-one ever had to care because the rename happens straight
afterwards.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209576 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-24 12:42:26 +00:00
NAKAMURA Takumi
4ca8b0b66d llvm/test/Object/ar-error.test: Don't check the message "No such file or directory".
It didn't match on non-English version of Windows.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209570 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-24 08:47:11 +00:00
Michael Zolotukhin
45788be6e2 Implement sext(C1 + C2*X) --> sext(C1) + sext(C2*X) and
sext{C1,+,C2} --> sext(C1) + sext{0,+,C2} transformation in Scalar
Evolution.

That helps SLP-vectorizer to recognize consecutive loads/stores.

<rdar://problem/14860614>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209568 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-24 08:09:57 +00:00
Tim Northover
6a04ef99f6 ARM64: extract a 32-bit subreg when selecting an inreg extend
After the load/store refactoring, we were sometimes trying to feed a
GPR64 into a 32-bit register offset operand. This failed in
copyPhysReg.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209566 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-24 07:05:42 +00:00