Commit Graph

14644 Commits

Author SHA1 Message Date
Nadav Rotem
0c8607ba6a Revert 172708.
The optimization handles esoteric cases but adds a lot of complexity both to the X86 backend and to other backends.
This optimization disables an important canonicalization of chains of SEXT nodes and makes SEXT and ZEXT asymmetrical.
Disabling the canonicalization of consecutive SEXT nodes into a single node disables other DAG optimizations that assume
that there is only one SEXT node. The AVX mask optimizations is one example. Additionally this optimization does not update the cost model.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172968 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 08:35:56 +00:00
David Blaikie
1426841672 The last of PR14471 - emission of constant floats
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172941 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 01:18:01 +00:00
Eric Christopher
0969ddf601 Split out DW_OP_addr for the split debug info DWARF5 proposal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172857 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-18 22:11:33 +00:00
Bill Wendling
1b0c54f1c5 Use AttributeSet accessor methods instead of Attribute accessor methods.
Further encapsulation of the Attribute object. Don't allow direct access to the
Attribute object as an aggregate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172853 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-18 21:53:16 +00:00
Bill Wendling
1a17bd21ff Remove unused parameter. Also use the AttributeSet query methods instead of the Attribute query methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172852 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-18 21:50:24 +00:00
Daniel Dunbar
6d49b680be [MC/Mach-O] Implement integrated assembler support for linker options.
- Also, fixup syntax errors in LangRef and missing newline in the MCAsmStreamer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172837 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-18 19:37:00 +00:00
Elena Demikhovsky
6c327f92a5 Optimization for the following SIGN_EXTEND pairs:
v8i8  -> v8i64, 
v8i8  -> v8i32, 
v4i8  -> v4i64, 
v4i16 -> v4i64 
for AVX and AVX2.

Bug 14865.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172708 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-17 09:59:53 +00:00
Eric Christopher
446b88fb81 Fix the assembly and dissassembly of DW_FORM_sec_offset. Found this by
changing both the string of the dwo_name to be correct and the type of
the statement list.

Testcases all around.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172699 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-17 03:00:04 +00:00
Eric Christopher
d96c72a14c Add the DW_AT_GNU_addr_base for the skeleton cu. Add support for
emitting the dwarf32 version of DW_FORM_sec_offset and correct
disassembler support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172698 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-17 02:59:59 +00:00
Jakob Stoklund Olesen
5ed625c3cf Move MachineTraceMetrics.h into include/llvm/CodeGen.
Let targets use it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172688 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-17 01:06:04 +00:00
Jakob Stoklund Olesen
02c6325a45 Provide a place for targets to insert ILP optimization passes.
Move the early if-conversion pass into this group.

ILP optimizations usually need to find the right balance between
register pressure and ILP using the MachineTraceMetrics analysis to
identify critical paths and estimate other costs. Such passes should run
together so they can share dominator tree and loop info analyses.

Besides if-conversion, future passes to run here here could include
expression height reduction and ARM's MLxExpansion pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172687 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-17 00:58:38 +00:00
Eric Christopher
6b6061f011 Define metadata interfaces for describing a static data member
of a class. Emit static data member declarations and definitions
through correctly.

Part of PR14471.

Patch by Paul Robinson!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172590 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-16 01:22:23 +00:00
Eric Christopher
72f7bfbf0e Split address information for DWARF5 split dwarf proposal. This involves
using the DW_FORM_GNU_addr_index and a separate .debug_addr section which
stays in the executable and is fully linked.

Sneak in two other small changes:

a) Print out the debug_str_offsets.dwo section.
b) Change form we're expecting the entries in the debug_str_offsets.dwo
   section to take from ULEB128 to U32.

Add tests for all of this in the fission-cu.ll test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172578 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-15 23:56:56 +00:00
Bill Schmidt
89e88e30bf This patch addresses an incorrect transformation in the DAG combiner.
The included test case is derived from one of the GCC compatibility tests.
The problem arises after the selection DAG has been converted to type-legalized
form.  The combiner first sees a 64-bit load that can be converted into a
pre-increment form.  The original load feeds into a SRL that isolates the
upper 32 bits of the loaded doubleword.  This looks like an opportunity for
DAGCombiner::ReduceLoadWidth() to replace the 64-bit load with a 32-bit load.

However, this transformation is not valid, as the replacement load is not
a pre-increment load.  The pre-increment load produces an extra result,
which feeds a subsequent add instruction.  The replacement load only has
one result value, and this value is propagated to all uses of the pre-
increment load, including the add.  Because the add is looking for the
second result value as its operand, it ends up attempting to add a constant
to a token chain, resulting in a crash.

So the patch simply disables this transformation for any load with more than
two result values.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172480 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-14 22:04:38 +00:00
Benjamin Kramer
4dc478308f When lowering an inreg sext first shift left, then right arithmetically.
Shifting right two times will only yield zero. Should fix
SingleSource/UnitTests/SignlessTypes/factor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172322 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-12 19:06:44 +00:00
Jakob Stoklund Olesen
6d6132986d Limit the search space in RAGreedy::tryEvict().
When tryEvict() is looking for a cheaper register in the allocation
order, skip the tail of too expensive registers when possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172281 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-12 00:57:44 +00:00
Jakob Stoklund Olesen
c7a275245f Precompute some information about register costs.
Remember the minimum cost of the registers in an allocation order and
the number of registers at the end of the allocation order that have the
same cost per use.

This information can be used to limit the search space for
RAGreedy::tryEvict() when looking for a cheaper register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172280 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-12 00:54:59 +00:00
Nadav Rotem
66de2af815 PPC: Implement efficient lowering of sign_extend_inreg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172269 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-11 22:57:48 +00:00
Benjamin Kramer
8ecd3be1f3 Remove some accidentaly duplicated code. This needs urgent cleanup :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172248 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-11 20:11:33 +00:00
Benjamin Kramer
69e42dbd00 Split TargetLowering into a CodeGen and a SelectionDAG part.
This fixes some of the cycles between libCodeGen and libSelectionDAG. It's still
a complete mess but as long as the edges consist of virtual call it doesn't
cause breakage. BasicTTI did static calls and thus broke some build
configurations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172246 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-11 20:05:37 +00:00
Nadav Rotem
3e40d927a7 ARM Cost Model: Modify the target independent cost model to ask
the target if it supports the different CAST types. We didn't do this
on X86 because of the different register sizes and types, but on ARM
this makes sense.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172245 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-11 19:54:13 +00:00
Eric Christopher
fffe363493 For inline asm:
- recognize string "{memory}" in the MI generation
- mark as mayload/maystore when there's a memory clobber constraint.

PR14859.

Patch by Krzysztof Parzyszek

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172228 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-11 18:12:39 +00:00
Andrew Trick
eed4e0193f Follow-up typo correction from building the wrong branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172224 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-11 17:51:16 +00:00
Andrew Trick
e9ccacd376 Fix typo from r170452. Affects -enable-misched heuristics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172223 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-11 17:46:50 +00:00
Tim Northover
5f2801bd65 Simplify writing floating types to assembly.
This removes previous special cases for each floating-point type in favour of a
shared codepath.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172189 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-11 10:36:13 +00:00
Evan Cheng
4ff23d09fa PR14896: Handle memcpy from constant string where the memcpy size is larger than the string size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172124 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-10 22:13:27 +00:00
Jakub Staszak
81bfd711de Remove unneeded includes from FunctionLoweringInfo.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172123 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-10 22:13:13 +00:00
Jakob Stoklund Olesen
4aebce8321 Allow hasProperty() to be called on bundle-internal instructions.
When calling hasProperty() on an instruction inside a bundle, it should
always behave as if IgnoreBundle was passed, and just return properties
for the current instruction.

Only attempt to aggregate bundle properties whan asked about the bundle
header.

The assertion fires on existing ARM test cases without this fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172082 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-10 18:42:44 +00:00
Jakob Stoklund Olesen
b11f050434 Support headerless bundles in MachineInstr::hasProperty().
This function can still work without a BUNDLE header instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172029 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-10 01:29:42 +00:00
Manman Ren
86441169da Stack Alignment: throw error if we can't satisfy the minimal alignment
requirement when creating stack objects in MachineFrameInfo.

Add CreateStackObjectWithMinAlign to throw error when the minimal alignment
can't be achieved and to clamp the alignment when the preferred alignment
can't be achieved. Same is true for CreateVariableSizedObject.
Will not emit error in CreateSpillStackObject or CreateStackObject.

As long as callers of CreateStackObject do not assume the object will be
aligned at the requested alignment, we should not have miscompile since
later optimizations which look at the object's alignment will have the correct
information.

rdar://12713765


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172027 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-10 01:10:10 +00:00
Nadav Rotem
14925e6b88 ARM Cost model: Use the size of vector registers and widest vectorizable instruction to determine the max vectorization factor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172010 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09 22:29:00 +00:00
Evan Cheng
78ec0255d9 Fix a DAG combine bug visitBRCOND() is transforming br(xor(x, y)) to br(x != y).
It cahced XOR's operands before calling visitXOR() but failed to update the
operands when visitXOR changed the XOR node.

rdar://12968664


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171999 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09 20:56:40 +00:00
Jakob Stoklund Olesen
ebed123c5c Don't print bundle flags.
The bundle flags are used by MachineBasicBlock::print(), they don't need
to clutter up individual MachineInstrs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171986 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09 18:35:09 +00:00
Jakob Stoklund Olesen
25377c8c6d Don't require BUNDLE headers in MachineInstr::getBundleSize().
It is possible to build MI bundles that don't begin with a BUNDLE
header. Add support for such bundles, counting all instructions inside
the bundle.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171985 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09 18:28:16 +00:00
Sergei Larin
12cd49ae1d Fix a typo in MachineInstr::unbundleFromSucc() method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171983 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09 17:54:33 +00:00
Tim Northover
2c8cf4b404 Refactor to expose RTLIB calls to targets.
fp128 is almost but not quite completely illegal as a type on AArch64. As a
result it needs to have a register class (for argument passing mainly), but all
operations need to be lowered to runtime calls. Currently there's no way for
targets to do this (without duplicating code), as the relevant functions are
hidden in SelectionDAG. This patch changes that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171971 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09 13:18:15 +00:00
Eric Christopher
1ced208be9 Last in the series of removing unnecessary '0' arguments for
address space. Reordered the EmitULEB128IntValue arguments to
make this easier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171949 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09 03:52:05 +00:00
Andrew Trick
47579cf390 MIsched: add an ILP window property to machine model.
This was an experimental option, but needs to be defined
per-target. e.g. PPC A2 needs to aggressively hide latency.

I converted some in-order scheduling tests to A2. Hal is working on
more test cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171946 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09 03:36:49 +00:00
Eric Christopher
68ca56285f These functions have default arguments of 0 for the last arg. Use
them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171933 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09 01:57:54 +00:00
Eric Christopher
ca1dd05c3c These functions have default arguments of 0 for the last arg. Use
them and add one where it seemed obvious that we wanted one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171932 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09 01:35:34 +00:00
Nadav Rotem
83be7b0dd3 Cost Model: Move the 'max unroll factor' variable to the TTI and add initial Cost Model support on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171928 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09 01:15:42 +00:00
Eric Christopher
b6714227ed Move the string pools down into the units. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171905 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-08 22:22:06 +00:00
Tim Northover
24d315dc05 Add fp128 rtlib function names to LLVM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171867 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-08 17:09:59 +00:00
Tim Northover
90f011e0ba Allow the asm printer to print fp128 values properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171866 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-08 16:56:23 +00:00
Chandler Carruth
40b2c32475 Sink a function that refers to the SelectionDAG into that library in the
one file where it is called as a static function. Nuke the declaration
and the definition in lib/CodeGen, along with the include of
SelectionDAG.h from this file.

There is no dependency edge from lib/CodeGen to
lib/CodeGen/SelectionDAG, so it isn't valid for a routine in lib/CodeGen
to reference the DAG. There is a dependency from
lib/CodeGen/SelectionDAG on lib/CodeGen. This breaks one violation of
this layering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171842 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-08 05:11:57 +00:00
Eric Christopher
9a1e0e252a Remove the llvm-local DW_TAG_vector_type tag and add a test to
make sure that vector types do work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171833 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-08 01:53:52 +00:00
Jakob Stoklund Olesen
6821060509 Pack MachineOperand bitfields better.
Previously, 4 bits were unused.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171814 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-07 23:21:44 +00:00
Jakob Stoklund Olesen
b2c79f2f63 Pack MachineInstr fields better.
This shrinks MachineInstr to 64 bytes (from 72).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171813 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-07 23:21:41 +00:00
Eric Christopher
ff34845f78 Whitespace and 80-col.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171803 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-07 22:40:45 +00:00
Eric Christopher
3cc4220560 Add more comments to what's going on here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171780 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-07 19:32:45 +00:00